JPS59231799A - Preventing device for foul writing to main memory - Google Patents

Abstract

PURPOSE:To prevent completely the foul writing and to improve the reliability by applying an interruption to a CPU when the writing is impossible with a subject address. CONSTITUTION:When a CPU21 performs writing to a main memory 22 in accordance with an execution instruction of the memory 22, a means 26 is provided to extract and store the writable address on the memory 22. The address stored in the means 26 is compared 27 and 28 with the subject address to be written by the CPU21. Then an interruption is applied to the CPU21 by the comparison output when the address to be written exceeds the range of the memory address. Thus the writing action is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for preventing unauthorized writing to a main memory device used in various devices equipped with a central processing unit.

Conventional configurations and their problems In general, when preventing unauthorized writing to the main memory in various devices equipped with a central processing unit, an unauthorized writing prevention device as shown in Figure 1 is often used. . First,
In the figure, 1 is the central processing unit J"1IVj location (hereinafter referred to as CI
), 2 is the address bus 5 f ;1r+
, a main memory device that stores desired data at a desired address based on the address information transmitted from the CPU 1. 3 is a write-protection device for setting an address that prohibits unauthorized writing to the main memory device 2. The address setting device 4 compares the address information transmitted to the main storage device 2 through the address bus 5 with the address information of the write-protection address setting device 3, and based on the result, writes from the C3PU 1. This is a comparison circuit that determines whether to transmit an interrupt command signal to the main storage device 2 or to supply an interrupt signal to 0PUI.
6 is a write command signal line that transmits a write command signal from the CPU 1 to the comparison circuit 4; 7 is a write command signal line that transmits a write command signal from the CPU 1 to the main storage device 2 through the comparison circuit 4; 8 An interrupt signal line 9 is used to transmit an interrupt signal from the comparison circuit 4 to the CPU 1, and an address bus 9 is used to transmit address information from the write-protection address setting device 3 to the comparison circuit 4.

It works just like that. First, when the CPU 1 attempts to execute a write operation to the main memory device 2, address information is transmitted from the CPU 1 to the main memory device 2 through the address bus 5, and at the same time, a write command signal line 6 is transmitted to the comparator circuit 4. A write command signal is applied through. Therefore, the comparison circuit 4 receives this command signal and compares the address information of the address bus 5 and the address log of the address bus 9,
Based on the result, write command signal line 7, interrupt signal IV
j! A required signal is output to any one of 8. Now, when the address information from the address bus 5 is larger than the address information from the address bus 9, the comparator circuit 4 outputs a write command signal from the CPU 1 to the write command signal line 7, and Address information is address bus 9
Assume that the configuration is such that an interrupt signal is output to the interrupt signal line 8 when the address information is smaller than the address information. In this case, address information from address bus 5 is transmitted to address bus 9.
ft j7 is smaller than the address information from , no data is output to the write command signal line 7, and no data is written to the main memory device 2. In this case, an interrupt signal is output to the interrupt signal line 8, so that the C
When PU1 receives an interrupt, it performs internal processing. If the address information from the address bus 5 is changed from the address information of the address bus 9, the write command signal is output to the write command signal line 7, so that the main memory device 2 is in a writable state. Desired data is written to each address corresponding to the address information from the address bus 5. In this way, even with conventionally used unauthorized write prevention devices, by setting an address (address) at which unauthorized writing is prohibited using the write-protection address setting device 3, unauthorized writing can be prevented from occurring below or above this address. It is possible to make it less common. however,
These types of unauthorized write prevention devices that have been used in the past only prevent unauthorized writing below or above a specific address set by the write-protection address setting device 3; Since there is no relationship with the execution command stored in the storage device 2, even if unauthorized writing is prevented below or above a specific address, the address based on the execution instruction stored in the main storage device 2 will not be the specified address. If the address is greater than or equal to or less than , it becomes possible to freely write to it, but if it is illegally written, the system will go down and its reliability will be significantly reduced.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned conventional drawbacks, and aims to provide an excellent fraud prevention device 6 with a simple configuration and high reliability. .

Structure of the Invention The present invention provides a method for determining when a central processing unit attempts to perform a 71 write operation on the main memory, from which address in the main memory the execution instruction is retrieved, and from which address to which address is written. A means is provided for extracting and storing whether the data is possible, and based on the address stored in the storage means, 1. Determine whether or not the address to which the central processing unit is actually attempting to write to the main memory is writable;
If writing is not possible, an interrupt is immediately issued to the central processing unit to prohibit unauthorized writing.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a schematic configuration diagram of an embodiment of a device for preventing unauthorized writing to a main storage device of the present invention, and 21 in the figure is a CPU 122.
24 is the main memory connected to the CPU 21 via the address bus 23, and 24 is the main memory 22 where the execution instruction is placed when the OPU 21 operates to write to the main memory 22. 25 is a temporary storage device that takes in and temporarily stores the value of the program counter through the address bus 23, when the 0PU 21 operates to write to the main storage device 22.
An execution instruction acquisition signal line 26 transmits an execution instruction acquisition signal output from the 0PU 21 to the temporary storage device 24, and the execution instruction acquisition signal line 26 is written in accordance with the value of the upper digit of the program counter value stored in the temporary storage device 24. Obtain the write permission table and set the upper limit of the writable address to the main storage device based on the write prohibition data transmitted through the write prohibition data setting line 29;
The auxiliary storage devices 27 and 28 that store the lower limit values compare the upper limit value and lower limit value of the write permission table stored in the storage device 26 with the output of the temporary storage device 30 of the write address to be described later. , an upper limit comparison circuit that does nothing if the output of the storage device 30 is within the range of the upper and lower limits, and applies an interrupt signal to the 0PU 21 via the interrupt line 32 when it exceeds the range; Lower limit comparison circuit, 30 is CPU2
When writing to the main storage device 22 by 1 is performed,
Temporary storage device 3 that writes and temporarily stores the address on the main storage device 22 to be written through the address bus 23;
1 is a write signal line that transmits a write signal to the temporary storage device 30 when 0PU21 writes 1 to the main storage device 22. When the 0PU 21 operates to write to the main memory 22 according to the actual instruction stored in the main memory 22, an execution instruction capture signal is output from the 0PU 21, and this is input to the program counter temporary memory 24. be done.

Therefore, in this state, the program counter temporary storage device 24 becomes ready for storage operation, and the value (that is, the value of the program counter) in the main storage device 22 in which the execution instruction was written is transferred to the program counter via the address bus 23. It is stored in the counter temporary storage device 24. The program counter temporary storage device 24 is configured to output the upper digit of the stored program counter value. For example, if the stored program counter value is address 23AO, the upper 1 digit of the stored program counter value is output. Outputs the value of “2”. Then, the value P2'' is applied to the auxiliary storage device 26, and the upper and lower limits of the writable address to the main storage device 22 are stored in the auxiliary storage device 26 based on the write-inhibited data from the CPU 21. Now, the main memory 21
The program counter value is 0 at address 23AO.
Assuming that it is stored that various data can be stored within the range from address 000 to address 0FFF,
The auxiliary storage device obtains its own write permission table based on the high-order digit “'2” of address 23AO, and the main storage device 2
Upper limit value cooo, lower limit value 01 of addresses that can be written to 2.
Remember FF.

On the other hand, when the actual write operation to the main memory device 22 by the CPU 21 starts, a write signal 31 is outputted from the CPU 2, and this is applied to the write signal temporary storage device 30 via the write signal line 3. be done. Therefore, in this state, the write signal temporary storage device 30 becomes ready for storage operation, and the address on the main storage device 22 to be written is transferred to the write signal temporary storage device 30 via the address bus 23.
The address is the upper limit value of the writable address that has been previously stored in the auxiliary storage device 26 by the upper limit comparison circuit 27 and the lower limit comparison circuit 28,
It is compared with the lower limit value, and it is determined whether the address to be written is within the range of the upper limit value and the lower limit value. ” If the address to be written is within the range of the above upper limit value and lower limit value, the comparison circuits 27 and 28 will not output any signals, and therefore 0PU21 is the address on the main memory device 22 to be written to. Enter the desired data into the address. If the address to be written exceeds the upper limit value or lower limit value, an interrupt signal is output from one of the comparator circuits 27 and 28,
This is applied to the CPU 21 via the interrupt signal line 32. Therefore, in this case C! The write operation by the PU 21 to the main storage device 22 is blocked, and so-called unauthorized writing is prohibited.

In this way, according to the above embodiment, the CPU'21 executes the instructions stored in the main memory 22 in accordance with the execution instructions stored in the main memory 22.
When writing to , the location on the main storage device 22 where the execution instruction is written is determined in advance.
A means is provided for extracting and storing information from which address to which address is writable on the main storage device 22, and the above address stored in this storage means and actually 0PU2] are stored in the main storage device 22. When the address to be written is compared and the output indicates that the address to be written exceeds the range of the stored address, C! PU] is configured so that no write operation is performed, and the writable address to the main storage device 22 completely matches the execution instruction stored in the main storage device 22, and the execution instruction is executed. It has the advantage that even if there are several cases, it can be made to correspond accurately.

Effects of the Invention As is clear from the embodiments described above, when a central processing unit receives an execution instruction stored in the main memory and attempts to write to the main memory according to the execution instruction, a first means for extracting and storing in advance at which address in the main storage device the execution command is stored and from which address to which address it is stored as writable, based on the above-mentioned medium-heat calculation; When the processing device actually starts writing to the main storage device according to the execution self-instruction, 1) a second storage means for extracting and storing an address on the main storage device to be written; 1st, 2nd
Comparing the addresses stored in the storage means, and interrupting the central processing unit when the address stored in the second storage means is outside the range of the address stored in the first storage means. , 2 J, E Ff12 A comparator circuit is provided to prevent writing to the storage device, and it is possible to completely prevent unauthorized writing according to the execution instructions stored in the main storage device, unlike the conventional method. This method has the advantage that the reliability of the entire system can be significantly improved compared to a system in which unauthorized write-protection numbers are set independently.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional unauthorized write prevention device. FIG. 2 is a schematic diagram of an embodiment of an unauthorized write prevention device for a main storage device according to the present invention. 21. Central processing unit, 22. Main storage device, 23.
・Address bus, 24. Program counter temporary storage device, 25.. Execution instruction capture signal line, 26.. Auxiliary storage device, 27.. Upper limit comparison circuit, 28.. Lower limit comparison circuit, 29.., writing. 3.. Temporary address storage device, 31.. Write signal line, 32.. Interrupt signal line.

Claims (1)

[Claims] When the central processing unit receives an execution instruction stored in the main memory and is about to write to the main memory according to the execution instruction, it determines in advance at which address in the main memory the execution instruction is written based on this. and a first means for extracting and storing from which address to which address 1 it is stored as writable, and the central processing unit actually writes data into the main storage device according to the execution command. a second storage means for extracting and storing an address on the main storage device to be written when writing is started;
, the addresses stored in the second storage means are compared, and when the address stored in the second storage means is outside the range of the address stored in the first storage means, the central processing unit A device for preventing unauthorized writing to a main memory device, which is provided with a comparison circuit that interrupts writing to the main memory device and prevents writing to the main memory device.