JPH0250749A - Information processor - Google Patents

Abstract

PURPOSE:To protect an extended register from a careless access from an application program by integrating a circuit which can be allowed to access an IO register added at the time of version up of a product only immediately after a specific command sequence in an address decoder. CONSTITUTION:The circuit which can be allowed to access the added IO register only immediately after a CPU has executed a certain specific command sequence is integrated in the address decoder. For instance, a command sequence 8 has two flip flops (FFs) 6, 7 and detects the execution of a specific command sequence. When the Q output of the FF 7 is defined as Q1, an access to the extended register 1 is validated only when Q1=1. Consequently, the IO register to be added at the time of version up of an information processor can be prevented from being destructed by a careless access from the application program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an IO address and memory address decoder section of a personal computer or the like. This article describes how to configure the address decoder for the 0 register and memory that are sometimes added to the product in order to expand its functionality when upgrading the version of the product.

[Background Art] An information processing device such as a personal computer usually has a central processing unit (hereinafter referred to as OPU), a memory, and an IO controller as its minimum components. Additionally, information processing device manufacturers regularly update their products, and at that time, new products often have some memory and controller functions added to conventional products. The present invention describes how to configure the memory and address decoder of the added part of the memory and the process controller when the functions of the memory and the process controller are added. Since the discussions are almost the same, all of the following explanations will be focused on the 0 controller. As an example of adding functions to the 0-controller, let us take the example shown in Fig. 3.

FIG. 3(α) is the address mapping of the old product KO-0 controller, and FIG. 3(b) is the address mapping of the new product KO-0 controller. IO address is 16
It is displayed in decimal numbers. Also, in this example, the address 0 is IO
It shall be bit. The Sunawachi 0 address space is 24 bytes of IO from 000 to 3FF. The old product has three controllers: a printer interface, a floppy disk interface, and an R82520 interface, but the new product will have an additional extension register (process0 address = 1BO).

The address decoder of the old product 0 controller is as shown in Figure 4. AEN is a DMA address enable signal, when AKN=1, DMA cycle, AEN=O
, it indicates that it is a CIPU cycle. XA
9 to XAO are address buses. IO1 IO2. I
O1 is an AND gate, and has printer interface, floppy disk interface, and R5, respectively.
2320 interface address is decoded. Figure 4 shows a commonly used address decoder. The expansion register added in new products and its address decoder have conventionally been configured as shown in Figure 5. In the figure, -X oW is a negative pole. Sex work 0 light pulse, x
D7 to XDO are data buses. 1 is an extension register, ]! ! X7 to EXO are its outputs. IO4 is a HAND gate, and the 0 address IBO (hexadecimal)
is decoded to create a write pulse for expansion register 1.

When adding functionality, a circuit like the one shown in FIG. 5 has been commonly used, but it has problems as explained below.

The IO address i BDH (hereinafter 16 numbers will be expressed by adding an H at the end of the number) is an address that is not used in the old product, so assign this unused address to the expansion register to be added. Since it was, there shouldn't be any problem. However, as a recent trend,
In the case of personal computers, etc., the hardware manufacturer that provides the product and the software manufacturer that provides the application program that runs on the product are separate, and the software manufacturer only needs to run the application program on the actual product. In some cases, they do not check the product specifications to see if they are being used in ways that do not meet the specifications. In many cases, all that is required is to ensure that the application program operates correctly on the product. Therefore, the I BOH of undefined address 0 in older products may be used carelessly. For example, it is possible that an IO write command to IBOH is executed in the middle of a program in order to insert a wait for time adjustment. In such a case, an application program created for the old product will not run correctly on the new product because it will destroy the added extension register (IO address 1: BDH). Functions added when upgrading from an old product to a new product will not be put to good use unless a new application program that uses the added functions comes out. However, many application programs created for old products must operate correctly on the new product as well as on the old product, even if the new product's enhanced functions are not taken advantage of. There is a risk that the circuit shown in FIG. 5 will not operate correctly.

FIG. 6 can be considered as an improved circuit of FIG. 5. IO
Reference numeral 6 denotes a flip 70 knob, which controls permission and prohibition of access to the expansion register 1. When the output of IO6 is 1, writing to the extension register 1 is permitted, and when the output is 0, it is prohibited. IO5 is a NAND gate that decodes address 1BFH and generates a write pulse to flip-flop IO6. IO7 is a NAND gate and generates a write pulse to the expansion register 1. IO7 is different from IO4 in FIG. 5, when the output of flip-flop 1o6 is IO, the address IB is
The condition that access to DH is possible is added. Writing 1 to bit 7 of IO address 1BIFH allows access to extension register 1, and writing 0 disables it. Normally, 0 is written, and access to extension register 1 is prohibited. Only when writing data to extension register 1, write 1 to bit 7 of IO address IBFH before writing data to extension register 1.
After the data has been written to, 0 is again written to bit 7 of address IBFH.

Although the circuit shown in FIG. 6 has improved some defects compared to the circuit shown in FIG. 5, it is still not satisfactory. If the application program carelessly executes a command that writes 1 to bit 7 of IO address 1BFH, the output of flip 70 block IO6 will remain 1 from then on. If the application program carelessly accesses the work address IBDH again after that, the contents of the extension register 1 will be destroyed. Although the probability is considerably lower than in Figure 5, it is still not perfect.

[Problems to be Solved by the Invention] The purpose of the present invention is to solve the above-mentioned problems, namely, when the work 0 register, which is added at the time of version upgrade of an information processing device, is destroyed due to careless access by an application program. The object of the present invention is to provide a device that solves the problem that the device may be stored away.

[Means for Solving the Problems] In the present invention, access to the added process 0 register is
It is characterized by incorporating a circuit into the address decoder that enables the PU to execute a certain command sequence only immediately after it has executed it.

[Example] The present invention will be explained below based on Examples.

FIG. 1 shows an embodiment of the present invention, and shows how to configure an extension register added to a new product and its address decoder. 1 is an expansion register, which is a register added to the new product. 2 is a NAND gate, which decodes the 0 address 1BDH and generates a write pulse to the expansion register 1. 6 and 4 are AND gates, and address 37BH and IBF respectively.
Decoding H. 5 is a NAND gate, O
When the PU executes an IO write command, it generates a pulse, which serves as the clock for the command sequencer 8. 8 is a command sequencer, which has two 7-lip-flops (hereinafter referred to as ?F) 6 and 7, and detects execution of a specific command sequence. ,'f
l XF Q output of 6 and 7 respectively. It is written as sQt. Ql is an input to NAND gate 2, and access to expansion register 1 is possible only when Q1=1.

The operation of the command sequencer 8 will be explained with reference to FIG. First of all, FF6 and FF7 are initially reset by the RESET signal, and Qo=Q+=0. This state is S. It is written as Command sequencer 8 clock is NA
The state of the command sequencer 8 changes only when the signal AEN=O and the signal -X0W=00, that is, when the CPU executes the write command. At other times, the previous state is maintained. In So, OPU sends an address to address 1BFH.
When the write command is executed, the output of AND gate 4 becomes 1.
Therefore, Qo=1. At this time, Ql remains 0. This Q. ``1*Q, 1=Suppose the state of the mouth is S.So
Even if a 0 write command is executed to a location other than IBFH, the command sequencer remains at So. Next, S.
In this state, when the write command to 57BH is executed, the output of the AND gate 3 becomes 1, and Q=1. Also, at this time, Qo returns to 0.

Let S be the state where Qo = Ot Q t = 1. S
, when executing the IO write command to other than 37BH at tlII, Qo ”Ot Q+ = 0 and So
It goes back to. In the state of S2, Q1=1, and NAND gate 2 is enabled only in this case. That is, in the state of S2, if the write command to IBDH is executed, the extension register 1 can be accessed.

If a write command is executed in state S, the state will always return to state So.

As mentioned above, in the circuit of FIG.
Access to is possible only in state S2. S
The state of , can be reached only by executing the IO write command to the machine 0 address IBFH followed by the IO write command to the machine 0 address 37BH, and furthermore, in this state of S, , data can be written to extension register 1 only when an IO write command to address IBDH is subsequently executed. That is, in order to write data to extension register 1 in the circuit shown in FIG. 1, the above three IO write commands must be executed successively. According to this method, accessing the extension register 1 becomes somewhat troublesome, but the extension register 1 can be protected from careless access by an application program. That is, the contents of the extension register 1 will be destroyed only if the application program accidentally executes the three zero-write commands in succession, but the probability of such a situation is almost zero.

[Effects of the invention] A circuit (encrypted code) that allows access to the process 0 register added at the time of product version upgrade only immediately after a specific command sequence (two IO write commands in Figure 1) By incorporating a circuit (which can be thought of as a circuit) into the Natres decoder, existing application programs (written for the product before the version upgrade) can ignore the process 0 register added in the new product. I was able to solve the problem of it breaking easily. According to the present invention, even if functions are expanded when a product is upgraded, a conventional application program can be operated without problems even on the new product.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention.
FIG. 3 is a diagram illustrating an operation of the command sequencer 8 in the figure. Figure 3 is a diagram showing an example of a product version upgrade, Figure 4 is a diagram showing an example of an address decoder in an old product, and Figures 5 and 6 are parts added in a new product ( FIG. 1...Extension registers 2, 5, IO4 e 1.05, IO7...
...NAND gate 5.4, IO1, IO2, IO3...AND gate 6.7, IO6...7 lip-flop 8,...
...Command sequencer Figure 1 16W/IBFI-1 Figure Figure Figure Figure (a) (b) Figure Figure Figure

Claims (1)

[Claims] (1) The register at a specific I@O@ address and the memory at a specific address in the I@O@ address space and memory address space can be accessed only immediately after executing a specific command sequence, and the above command An information processing device that is inaccessible unless a sequence is executed.