JPS62243059A - 記憶制御方式 - Google Patents

記憶制御方式

Info

Publication number
JPS62243059A
JPS62243059A JP8590386A JP8590386A JPS62243059A JP S62243059 A JPS62243059 A JP S62243059A JP 8590386 A JP8590386 A JP 8590386A JP 8590386 A JP8590386 A JP 8590386A JP S62243059 A JPS62243059 A JP S62243059A
Authority
JP
Japan
Prior art keywords
data
request
read
ram
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8590386A
Other languages
English (en)
Japanese (ja)
Other versions
JPH054709B2 (enrdf_load_html_response
Inventor
Yasuhiko Matsuura
松浦　泰彦
Junichi Takuri
田栗　順一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8590386A priority Critical patent/JPS62243059A/ja
Publication of JPS62243059A publication Critical patent/JPS62243059A/ja
Publication of JPH054709B2 publication Critical patent/JPH054709B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP8590386A 1986-04-16 1986-04-16 記憶制御方式 Granted JPS62243059A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8590386A JPS62243059A (ja) 1986-04-16 1986-04-16 記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8590386A JPS62243059A (ja) 1986-04-16 1986-04-16 記憶制御方式

Publications (2)

Publication Number Publication Date
JPS62243059A true JPS62243059A (ja) 1987-10-23
JPH054709B2 JPH054709B2 (enrdf_load_html_response) 1993-01-20

Family

ID=13871806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8590386A Granted JPS62243059A (ja) 1986-04-16 1986-04-16 記憶制御方式

Country Status (1)

Country Link
JP (1) JPS62243059A (enrdf_load_html_response)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006221432A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165287A (ja) * 1983-03-11 1984-09-18 Nec Corp 情報処理システム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165287A (ja) * 1983-03-11 1984-09-18 Nec Corp 情報処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006221432A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置

Also Published As

Publication number Publication date
JPH054709B2 (enrdf_load_html_response) 1993-01-20

Similar Documents

Publication Publication Date Title
US6480927B1 (en) High-performance modular memory system with crossbar connections
US5581767A (en) Bus structure for multiprocessor system having separated processor section and control/memory section
CN100595720C (zh) 用于基于集线器的存储系统中直接存储器访问的设备和方法
US5577204A (en) Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device
JP2501419B2 (ja) 多重プロセッサメモリシステム及びメモリ参照競合解決方法
KR970029014A (ko) 데이타 프로세싱 시스템 및 방법
JPH03500585A (ja) トロイダル接続された分布記憶装置型並列計算機のための増強された入出力アーキテクチャ
JP2000268006A (ja) マルチプロセッサシステム
JPH1049482A (ja) ピア・ツー・ピア・サポートを有する２重ホスト・ブリッジ
US6546465B1 (en) Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
JP4975288B2 (ja) 共有メモリ装置
JP2561261B2 (ja) バッファ記憶アクセス方法
JPH04230558A (ja) ダイレクト・メモリ・アクセス装置
US6308244B1 (en) Information processing apparatus with improved multiple memory access and control
US5367701A (en) Partitionable data processing system maintaining access to all main storage units after being partitioned
JP2006294049A (ja) ランダムアクセス方法において並列プロセッサに分配する前のシーケンシャルデータの分類
JPS62243059A (ja) 記憶制御方式
JPH09506731A (ja) マルチプロセッサ・システム用バス構造
JPH0281255A (ja) マルチプロセッサコンピュータ複合装置
US7484052B2 (en) Distributed address arbitration scheme for symmetrical multiprocessor system
JP4112954B2 (ja) 磁気ディスク記憶制御装置
JP2598441B2 (ja) ベクトルデータ処理装置
JPS59218532A (ja) バス接続方式
JPH0750466B2 (ja) 並列計算機キャッシュ・メモリ制御方式
JP2976700B2 (ja) プロセッサ間同期制御方式