JPS62232065A - Synchronization system for plural processors - Google Patents

Abstract

PURPOSE:To easily synchronize plural processors by constituting the title system so that the operation of one processor group is started only at the time when the synchronization control signals from the processors in another group come in the same level. CONSTITUTION:The flags 2b, 2c, ..., 2n of subprocessors 1b, ..., 1n are connected to the common line 3 via open collector type buffers 7b, 7c, ..., 7n. The line 3 is connected to the flag 2a of a master processor 1a. Accordingly, if the output of either one of the flags 2b-2n is in level 'L', the line 3 is made also in the level 'L' via the buffer 7, and the flag 2a of the master processor 1a is set in 'L'. Also, if all the outputs of the flags 2b-2n of the subprocessors 1b-1n come in level 'H', the line 3 comes in also in level 'H', and 'H' is set in the flag 2a of the master processor 1a.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to processing vc′ of a plurality of microprocessors, etc.
11 in parallel, each processing device rI
This invention relates to a method for enabling synchronization of IIll.

Prior Art Generally, in an information processing system, for example, when a plurality of printed circuit boards are each equipped with a microprocessor,
Depending on the program to be executed, it is necessary to synchronize each microprocessor. In conventional information processing systems, synchronization between multiple microprocessors is accomplished using input/output lines.
Therefore, for example, when attempting to synchronize these in a system using l microprocessors, it is necessary to prepare bits, or bins, into which the synchronization control number 13 of the remaining n-1 processors is input for each processor. However, the functions of such microprocessors are greatly restricted, and a great deal of effort is required for interconnecting the n-1 bins of each of these microprocessors.

Furthermore, in a system using a predetermined number of microprocessors, when attempting to expand the system by increasing the number of microprocessors, it becomes necessary to newly allocate the bin for synchronization control to each microprocessor. It was impossible to expand the system.

Problems to be Solved by the Invention It is an object of the present invention to solve the above-mentioned problems and to provide a system that can realize synchronous control of an arbitrary number of processing devices with a simple configuration, and that can be performed by adding processing devices. An object of the present invention is to provide a synchronization method for a plurality of processing devices that can easily realize expansion.

Means for Solving the Problems The present invention provides that one group of a plurality of processing devices is each provided with a synchronous control M signal generation section, and the other group of processing devices is provided with a receiving section to which a synchronous control signal is commonly applied. are provided respectively, and the above J! l! The other group of V devices is a synchronization method for a plurality of processing devices, characterized in that the operation mode is switched when the synchronization control signals from the processing devices of the -blade group are at the same level.

According to the present invention, the plurality of processing devices are divided into one group and the other group, - the blade groups are each provided with a synchronous control signal generator, and the other group is commonly given a synchronous control signal. A receiving section is provided, respectively.C).

Further, the other group of processing devices switches the operation mode when the synchronization control signals from the processing devices of the second group are at the same level.

Therefore, to connect the blade group and the other group, it is sufficient to connect the line to which the synchronization control signal of the blade group is commonly given to the other group of the processing device, and therefore the blade group's processing r. ! , when increasing the number of devices, it is sufficient to connect the synchronization control signal generating section of the processing device to be added to the i line. Therefore, synchronization of such processing devices can be realized with a simple configuration. Even when adding devices, this can be easily achieved.

Embodiment Figure Pt51 is a block diagram showing the basic configuration of an embodiment of the present invention, and Figure ttS2 is a block diagram showing the configuration of an embodiment of the present invention. The configuration of this embodiment will be explained with reference to Figure 151 and Figure Pt42.

In this embodiment, a microprocessor 1a, which is a processing device,
In this embodiment, the microprocessor 1a in which IL+, lc, . . . +in is used is called a mask processor,
The remaining microprocessors 11+ to in are referred to as subprocessors. That is, in this embodiment, the operating state of the mask processor 1a is switched for the first time when the synchronization side all signals, which will be described later, from each sub-processor lb-in become at the same level.

Each of the microprocessors 1a to 111 is in an operable state, that is, Read.
Flags 2a, 2b indicating whether the state is y.

... are provided respectively. When each microprocessor 1 enters the Ready state, this 7 lag 2 indicates that, for example, "tlJ is set and it is not in the Ready state."
LJ is set. This flag 2 a+'2 bl・
. . are connected in common to line 3, and for mask processor 1a, only input is made from line 3 to flag 2m, and for the remaining sub-processors 11+, . . . only output is made to line 3. Such a 7lug 2 is a so-called 11red-O as described later.
R is connected.

In addition, each microprocessor 1 has its own operating state,
In other words, a suspension of operation! ! ! ! Further, status registers 4m, 4b, . . . are provided in which information representing the status of various types of processing in progress is written, and these registers are connected to the bus 5 in a freely input/output manner. A pull-up resistor 6 is connected to the line 3, and a reference voltage Vcc is connected thereto.

FIG. 3 is a diagram illustrating the principle of wired-OR connection of line 3 described in Section 1. With reference to FIGS. 1 and 3,
The wired-OR connection will be explained.

7 lags of subprocessors lb,..., Ill 2 b,
2 c...

211 is an open collector type buffer T7.
b, 7 c, . . . , common line 3 via 70
and this line 3 is connected to mask processor 1
It is connected to 7 lug 2a of a. Therefore each 7 lugs 2b
If even one of the outputs of ~20 lags is rLJ, the line 3 becomes "L" level through the corresponding buffer 7, and therefore the 7 lag 2 of the mask processor 1a
u is set to rLJ. On the other hand, sub-processor 11
When all the 7 lags 2b to 211 of I to 111 output "■("), line 3 also enters the "■I" state, and "■1" is set to the 7 lags 2a of the mask processor 1a.

FIG. 4 is a block diagram 70- explaining the operation of the mask processor 1a.
The tiS5 diagram shows each subprocessor IL+
It is a flowchart explaining the operation of +....

The operation of this embodiment will be explained with reference to FIGS. 1 to 5s. Each step o1 in FIGS. 4 and 5. I
At 61, the master processor 1a and the sub-processors lb, . Subsequently, when each sub-processor lb,... becomes operational, its own 7 lag 2L+,...
"Set to IIJ.

As mentioned above, since the 7 lags 2b, . . . of each sub-processor Ib, . Yes or no 4
'qIrR is total? 17'O set 1b+・=+1n
This is equivalent to the t1 disconnection when all 7 Raku 2b, . . . are set to rtlJ.

Therefore, if the judgment is negative in step n2 of the m4 diagram, the flag of each subprocessor lb,...+1n is in the f'LJ state, and the subprocessor is not in an operable state. On the other hand, each sub-processor lb,..., in the status reno star 4, etc. of the sub-processor lb,..., in.

The above-mentioned operating state at the time of the inquiry of 111 is described.

If the judgment in step 112 is positive, the process moves to step n3, where the mask processor 1a makes itself operational and writes this information to the status recorder 4a.In this way, the master processor 1a
becomes operational only when all remaining sub-processors lb, .
It is possible to start various operations in synchronization with...

Further, in step 12 of FIG. 5, each sub-processor Ib, . . . reads the contents of the status recorder 4a of the master processor 1a, and starts various processes in accordance with the contents.

On the other hand, Fig. 1 and ? Even when adding a sub-processor as explained with reference to the tS2 diagram, expansion can be achieved by connecting the 7 lugs 2 and status reno star 4 provided in the added sub-processor to line 3 and bus 5, respectively. is realized, making it easy to expand the system.

Effects As described above, according to the present invention, one group of a plurality of processing devices is each provided with a synchronous control signal generating section, and the other group is each provided with a receiving section to which the same Wi-control rnJ signal is commonly given. I made it possible to do so. *If Note: The other group of each processing device switches its operation mode when the eight synchronized signals from the processing device of one group are at the same level.

Therefore, the operation of the processing device of the blade group starts at the location of the other group J! I! It is executed only when the synchronization control signals from the devices are each at the same level, and in this way synchronization of a plurality of processing devices can be easily realized.

[Brief explanation of drawings]

Fig. Pt51 is a block diagram showing the basic configuration of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. fjS3 is a block diagram explaining the principle of wired-OR connection of flags 2m-2n, Fig. 4 The figure is a 70-chart explaining the operation of the master processor 1a, and FIG. 5 is a sub-processor 1b.
7a-chart explaining the operation of , . 1a...mask processor, lb,..., 10...
・Subprocessor, 2...Flag, 3...Line,
4...Status Renosta, 5...Bus

Claims (1)

[Scope of Claims] One group of the plurality of processing devices is each provided with a synchronous control signal generating section, the other group of processing devices is each provided with a receiving section to which the synchronous control signal is commonly given, and the processing A method for synchronizing a plurality of processing devices, characterized in that the other group of devices switches the operation mode when the synchronization control signals from the processing devices of the first group are at the same level.