JP2954019B2 - Logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation system, and more particularly to a logic simulation system for simulating a logic circuit at high speed.

[0002]

2. Description of the Related Art Conventionally, this kind of logic simulation method is used for performing a logic simulation of a logic circuit at a high speed. For example, a circuit for performing a simulation by dividing a logic circuit to be simulated into a plurality of logic circuits. There is a division method.

In this circuit division method, a logic circuit to be simulated is divided into a plurality of logic circuits by deciding an interface so that the exchange of signals between the divided logic circuits is reduced, and each of these divided circuits is determined. The logic circuit is created with dedicated hardware. Simulation is performed by operating these dedicated hardware and transmitting the change in the interface of each operated dedicated hardware to other dedicated hardware while synchronizing these dedicated hardware.

[0004]

In the above-described conventional logic simulation method, a change in the interface of each dedicated hardware is transmitted to other dedicated hardware while synchronizing between these dedicated hardware. This requires a waiting time until the transfer and a transmission time for transmitting the change of the interface. Depending on the method of dividing the logic circuit to be simulated, the waiting time and the transmission time increase, and the simulation can be performed at high speed. There is a problem that it may not be possible to do so. In addition, since the logic circuit to be simulated is divided into a plurality of logic circuits and each of the divided logic circuits is operated on dedicated hardware for simulation, dedicated hardware corresponding to the number of divided circuits is required. There is a problem that costs are high.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulation method capable of performing a simulation at a high speed and eliminating cost in order to eliminate such a conventional drawback.

[0006]

According to the logic simulation method of the present invention, a simulation load module having a simulation program for simulating the operation of a logic circuit and logic information of the logic circuit, and an input signal input to the logic circuit are provided. Input means for inputting an input pattern indicating a set of logical patterns; and specifying a reference signal from among the input signals corresponding to the logical pattern included in the input pattern, and corresponding to the specified signal. Division input pattern creation means for dividing the input pattern along a time axis with reference to the time when the logic value of the logic pattern changes to create the plurality of division input patterns; and inputting the plurality of division input patterns Within the time width of each of the inputted divided input patterns, the reference signal The logical value of the corresponding logical pattern and the logical pattern corresponding to the signal other than the reference signal included in the input signal alone is used to find a logical element in the logical circuit whose initial value is not uniquely determined. Initial value setting means for setting the initial value of the logic element found for each divided input pattern and outputting it as an initial value setting file, each of the plurality of divided input patterns,
Transfer means for transferring to the plurality of second execution means together with the simulation load module and the initial value setting file, each receiving the simulation load module, the initial value setting file and the divided input pattern, A plurality of second execution means for simulating the received divided input pattern using the simulation load module and the initial value setting file; and a plurality of second execution means; Integrated output means for integrating and outputting the simulation results of the respective execution means.

Further, in the logic simulation method according to the present invention, the simulation load module, the initial value setting file, and the divided input pattern are respectively received, and the simulation load module and the divided load pattern are received in response to the received divided input pattern. A plurality of second processing units having the second execution unit for performing simulation with the initial value setting file; and the simulation program having the simulation program for simulating the operation of the logic circuit and logic information of the logic circuit. Input means for inputting a load module and the input pattern indicating a set of logical patterns of the input signals to be input to the logic circuit; and among the input signals corresponding to the logical patterns included in the input pattern input, Finger reference signal Dividing input pattern creating means for creating the plurality of divided input patterns by dividing the input pattern along a time axis based on a time at which a logical value of the logical pattern corresponding to the designated signal changes; A plurality of divided input patterns are input, and within the time width of each of the input divided input patterns, a signal other than the reference signal included in the logic pattern and the input signal corresponding to the reference signal is input. An initial value setting file which searches for logical elements in the logical circuit whose initial value is not uniquely determined only by the logical value corresponding to the logical pattern and sets initial values of the searched logical elements for each of the divided input patterns. Initial value setting means for outputting each of the plurality of divided input patterns as the simulation load module and the initial value. A first process including: a transfer unit that transfers each of the simulation results of the plurality of second processing devices together with a setting file to each of the plurality of second execution units; And a device.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a logic simulation system according to the present invention.

The present embodiment shown in FIG.
An input means 1 for inputting a simulation load module having a simulation program for simulating the operation of the logic circuit and logic information of the logic circuit 12 and an input pattern 13 indicating a set of a logic pattern 14 of an input signal to be input to the logic circuit 12; A reference signal is designated from input signals corresponding to the logic pattern 14 included in the input pattern 13 and the input pattern is determined based on the time when the logic value of the logic pattern 14 corresponding to the designated signal changes. 13 is divided along the time axis to generate a plurality of divided input patterns 15, and a first simulation is performed for each of the plurality of divided input patterns 15 in parallel by a simulation load module. And the first execution means 3 Is constituted by an integrated output means 7 for outputting the combined their results were down.

The first execution means 3 receives a plurality of divided input patterns 15 and, within a time width of each of the inputted divided input patterns 15, a logical value of a logical pattern 14 corresponding to a reference signal. The logic circuit 12 whose initial value is not uniquely determined only by the logic value of the logic pattern 14 corresponding to a signal other than the reference signal included in the input signal.
The initial value setting means 4 for setting the initial values of the found logical elements for each divided input pattern 15 and outputting as an initial value setting file, and each of the plurality of divided input patterns 15 Transfer means 5 for transferring the load module and the initial value setting file together with the load module for simulation, the initial value setting file, and the divided input pattern 15 from the transfer means 5; And a plurality of second execution means 6 for simulating with a simulation load module and an initial value setting file.

Next, the operation of the logic simulation system according to the present embodiment will be described in detail with reference to FIGS. 2, 3, 4 and 5.

FIG. 2 is a diagram showing an example of a logic circuit to be simulated. A plurality of input signals IN input to a logic circuit 12 having a plurality of logic elements a and b are shown.
The figure shows that a to INp are converted by the logic elements a to b and output as a plurality of output signals OUTa to OUTq.

FIG. 3 is a diagram showing an example of the relationship between an input pattern and a divided input pattern. An input pattern 13 is an input signal I to be input to the logic circuit 12 to be simulated.
Each of the input patterns 13 is made up of a logical pattern a14a to a logical pattern p14p obtained by patterning each of Na to INp with respect to the time axis.
It is shown that the input data is divided into a plurality of divided input patterns a15a to s15s at each rising time point of 14a. In addition, these divided input patterns 15
Generally have different time widths, however, here, the description will be made assuming that the reference signal INa is a signal of a fixed period and the time widths T of the divided input patterns 15 are all the same.

FIG. 4 is a diagram showing an example of a partial pattern which is a minimum unit to be simulated. The divided input pattern 15 is divided for each unit time t, and a plurality of partial patterns 16 (the number of partial patterns is 500). ~ 5000,
Here, for example, the partial pattern t1 to the partial pattern t1
Description will be made assuming 0. ), And each partial pattern 16
Indicate that simulation is performed in the order of the partial pattern t1 to the partial pattern t10 using the respective values of the logical pattern a14a to the logical pattern p14p.

FIG. 5 is a diagram showing an example when the simulation results are integrated, and the simulation result when the input pattern 13 is divided into a plurality of divided input patterns 15 of divided input patterns a15a to s15s. Is shown to be integrated. (1) in FIG.
The simulation result of the divided input pattern a15a is shown, and the input signals INa-INp and the output signals OUTa- are shown in FIG. OUTq respectively. (2) of FIG. 5 shows a simulation result of the divided input pattern s15s, similarly to (1) of FIG.
FIG. 5 (3) shows that the simulation results of the divided input patterns a15a to s15s shown in (1) to (2) of FIG. 5 are arranged and integrated. I have.

In FIG. 1, a simulation load module having a simulation program for simulating the operation of the logic circuit 12 shown in FIG. An input pattern 13 shown in FIG. 3 corresponding to an input signal input to the circuit 12 is input. Here, the logical information of the logic circuit 12 indicates designation of a type of a logic element used in the logic circuit 12, designation of its operation, information on connection between logic elements used in the logic circuit 12, and the like.

The divided input pattern creating means 2 includes an input means 1
By reading a reference signal from the input signals corresponding to the respective logical patterns 14 included in the input pattern 13 input from the reference signal file 8 in which signal names to be used as references are stored in advance, Alternatively, a signal name to be used as a reference is specified by directly inputting from an input device 10 such as a keyboard (here, for example, INa is specified), and the logical value of the logical pattern a14a corresponding to the specified signal INa is, for example, "". The input pattern 13 is divided along the time axis as shown in FIG. 3 on the basis of the time when the value changes from “0” to “1”, and a plurality of divided input patterns 15 are created.

The initial value setting means 4 corresponds to the reference signal INa in the first partial pattern t1 shown in FIG. 4 for each of the plurality of divided input patterns 15 created by the divided input pattern creating means 2. Logical pattern a1
A logic element in the logic circuit 12, such as a flip-flop, whose initial value is not uniquely determined only by the logic value of the logic pattern 4a and the logic value of the logic pattern 14 corresponding to the signal other than INa included in the input signal, The simulation program in the simulation load module is executed for the portion of the partial pattern t1 to find the initial value corresponding to the found logic element.
The initial values of the logic elements are read from an initial value file 9 storing the initial values of the logic elements in advance, or the initial values of the logic elements are directly input from an input device 11 such as a keyboard. Set the value and output this as the initial value setting file.

The transfer means 5 includes a divided input pattern creating means 2
Are transferred to the plurality of second execution units 6 together with the simulation load module input from the input unit 1 and the initial value setting file output from the initial value setting unit 4 respectively. I do.

Each of the plurality of second executing means 6 receives the simulation load module, the initial value setting file, and the divided input pattern 15 transferred from the transferring means 5, respectively. ,
For the logical element whose initial value is not uniquely determined in the first partial pattern t1 shown in FIG. 4, the initial value corresponding to this logical element is read from the initial value setting file and set. Then, the simulation program in the simulation load module is executed, and the divided input pattern 15 is simulated in the order of the partial pattern t1 to the partial pattern t10 shown in FIG.

The integrated output means 7 outputs the result of the simulation executed by each of the plurality of second execution means 6 in FIG.
And output as integrated.

In the above description, each means constituting an example of the logic simulation system of the present invention is not assigned to a specific processing device. However, as shown in FIG. The apparatus 20 is provided with input means 1, divided input pattern creation means 2, initial value setting means 4, transfer means 5 and integrated output means 7, and is provided with a general-purpose second station such as a plurality of workstations.
May be provided with the second execution means 6. Also, as shown in FIG. 7, the second execution means 6 may be added to the first processing device 20 having the configuration shown in FIG.

[0024]

As described above, according to the logic simulation method of the present invention, the input signal is shifted with respect to the time axis.
A plurality of divided input patterns are created by dividing the input pattern indicating the set of patternized logical patterns along the time axis, and each of these divided input patterns is simulated in parallel, and the results are integrated. To do
I will get the simulation result of this input pattern
To simulate the input pattern at high speed.
Can be In addition, since this simulation can be performed by a general-purpose processing device such as a workstation, it is not necessary to create dedicated hardware, and the cost is not increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a logic simulation method according to the present invention.

FIG. 2 is a diagram illustrating an example of a logic circuit to be simulated;

FIG. 3 is a diagram illustrating an example of a relationship between an input pattern and a divided input pattern.

FIG. 4 is a diagram illustrating an example of a partial pattern that is a minimum unit to be simulated.

FIG. 5 is a diagram showing an example when integrating simulation results.

FIG. 6 is a diagram illustrating an example of a configuration of a general-purpose processing device.

FIG. 7 is a diagram illustrating another example of the configuration of the general-purpose processing device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 input means 2 divided input pattern creation means 3 first execution means 4 initial value setting means 5 transfer means 6 second execution means 7 integrated output means 8 reference signal file 9 initial value file 10, 11 input device 12 logic circuit 13 Input pattern 14 Logic pattern 14a to 14p Logic pattern a to Logic pattern p 15 Divided input pattern 15a to 15s Divided input pattern a to Divided input pattern s 16 Partial pattern 20 First processing device 21 Second processing device

Claims (3)

(57) [Claims] 1. A simulation load module having a simulation program for simulating the operation of a logic circuit and logic information of the logic circuit, and an input pattern indicating a set of logic patterns of input signals input to the logic circuit are input. Input means; the input signal corresponding to the logical pattern included in the input pattern
Specify the reference signal from the signals and specify the specified signal
The time at which the logical value of the logical pattern corresponding to
Division input pattern creating means for dividing the input pattern along a time axis with reference to create a plurality of divided input patterns; and inputting and inputting the plurality of divided input patterns
Within the time width of each of the divided input patterns, the reference
And the logical value of the logical pattern corresponding to the signal to be
For signals other than the reference signal included in the input signal,
Only the logical value of the corresponding logical pattern and its initial value
Finds a logic element in the logic circuit that is not uniquely determined
Then, the initial values of the found logic elements are
First to set for each pattern and output as an initial value setting file
Term value setting means, and each of the plurality of divided input patterns
Load module and the initial value setting file
Transfer means for transferring to the plurality of second execution means together with
Stages, each with the load module for simulation
Receiving the initial value setting file and the divided input pattern
The received divided input pattern
Load module and the initial value setting file
The plurality of second executing means simulating by
First execution means and comprising the a; plurality of second execution hand
Integrated output means for integrating and outputting the simulation results of each stage . 2. A load module for simulation.
Module, initial value setting file and split input pattern
The received divided input pattern
Load module and the initial value setting file
Having a second execution means for simulating by
Number of second processing units; simulating the operation of the logic circuit
Simulation program and the logic circuit
The load module for simulation having logic information
Module and a logical pattern of an input signal input to the logic circuit.
Input means for inputting an input pattern indicating a set of patterns, and the logical pattern included in the input pattern
Designate a reference signal from the corresponding input signals
The logic of the logic pattern corresponding to the specified signal
The input pattern is time-axis based on the time when the value changes.
Divided along to create multiple divided input patterns
Force pattern creating means, and inputting the plurality of divided input patterns,
Within the time width of each of the divided input patterns,
Included in the logic pattern corresponding to the input signal and the input signal.
Said theory corresponding to signals other than the reference signal
Only the logical value with the logical pattern determines the initial value uniquely.
Search for logic elements in the logic circuit that do not
The initial value of the extracted logic element is set for each of the divided input patterns.
Initial value setting means to specify and output as an initial value setting file
And each of the plurality of divided input patterns
Load module and the initial value setting file
Together with the transfer to each of the plurality of second execution means.
Sending means, and simulation of each of the plurality of second processing devices.
A first processing device comprising: integrated output means for integrating and outputting the result ; 3. A load module for simulation.
Module, initial value setting file and split input pattern
The received divided input pattern
Load module and the initial value setting file
Having a second execution means for simulating by
Number of second processing units; a simulation program for simulating the operation of a logic circuit ; a load module for simulation having logic information of the logic circuit; and an input indicating a set of logic patterns of input signals to be input to the logic circuit. Input means for inputting a pattern, and a reference signal is designated from among the input signals corresponding to the logic pattern included in the input pattern, and a logic value of the logic pattern corresponding to the designated signal changes. Divided input pattern creating means for creating the plurality of divided input patterns by dividing the input pattern along a time axis on the basis of the time to be input, and inputting the plurality of divided input patterns and inputting each of the divided inputs Within the time width of the pattern, the logic pattern corresponding to the reference signal and the input signal Only the logical value of the logical pattern corresponding to the signal other than the reference signal is searched for a logical element in the logical circuit whose initial value is not uniquely determined, and the initial value of the logical element found is searched for. Initial value setting means for setting for each divided input pattern and outputting as an initial value setting file; and each of the plurality of divided input patterns to a plurality of second executing means together with the simulation load module and the initial value setting file. Transfer means for transferring, respectively, the simulation load module, the initial value setting file, and the divided input pattern, and the received divided input pattern is simulated by the simulation load module and the initial value setting file. said second execution means for, second processing of said plurality Logic simulation method characterized by comprising; an integrated output means for integrating each of the simulation results of the device and said second execution unit, a first processing unit having a.