JP4205525B2 - Parallel simulation apparatus and parallel simulation method - Google Patents

Description

  The present invention relates to an LSI parallel simulation technique, and more particularly to a parallel simulation apparatus and a parallel simulation method for parallel simulation of an LSI function having a clock having a plurality of frequencies.

  In recent years, the scale of LSI circuits has been increasing, and it has become unavoidable to extend the development period. Accordingly, the scale of software operating on LSIs is increasing, and early development of software is desired.

  In order to develop software that operates on an LSI, it is necessary to use the LSI. However, if the development of the LSI is awaited, there is a risk that the appropriate sales time of a product that uses the LSI will be missed. .

  Therefore, as an alternative to LSI, a software simulator for simulating LSI functions with software, an emulator that implements the LSI functions using hardware such as FPGA, and combinations thereof are provided. . By using these, development of software that operates on the LSI and system evaluation can be started at an early stage without waiting for completion of the development of the LSI.

  For an LSI simulator, an increase in the LSI circuit scale has the effect of reducing the function simulation speed. As a countermeasure, a method of simulating each function in an LSI circuit in parallel with a plurality of computers has been conventionally employed.

  Conventionally, there are two methods for parallelization in function simulation. The first is an event-driven method that operates only when the value of a certain signal changes. The second method operates according to a given input in synchronization with a certain time and operates until the signal value does not change. (For example, see Patent Document 1).

The iterative method can be further classified into the following two forms.
(1) Synchronous type: A simulation method that executes data synchronization processing between computers in the finest time management unit when performing parallel simulation.
(2) Asynchronous type: A shredding method in which, when performing parallel simulation, a computer independently manages time and executes data synchronization processing with another computer at an appropriate time.

  Hereinafter, an iterative asynchronous parallel simulation will be taken as a conventional method, and an embodiment thereof will be described with reference to the drawings. Here, it is assumed that the function in the LSI operates with a plurality of clocks.

  FIG. 1 is a block diagram showing an embodiment of a parallel simulation apparatus according to a conventional method. In FIG. 1, a parallel simulation apparatus 100 includes a computer 110 and a computer 120 that share the simulation of the internal functions of an LSI, and a network 130 that connects them.

  In the conventional LSI function simulation with the above configuration, the computer 110 executes a high-speed function simulation 111 that operates with a high-speed clock and a low-speed function simulation 112 that operates with a low-speed clock.

  Similarly, the computer 120 also executes a high-speed function simulation 121 that operates with a high-speed clock and a low-speed function simulation 122 that operates with a low-speed clock. The computer 110 and the computer 120 exchange information via the network 130 to realize parallel simulation of LSI functions.

  FIG. 3 is a flowchart of parallel simulation of LSI functions according to the conventional method. In the flowchart of FIG. 3, the same reference numerals are assigned to the simulations shown in FIG. 1 to indicate that the processing contents are the same. The computer 110 and the computer 120 have the same flow of processing although the simulation contents are different, so the flowchart in the computer 110 will be described below.

  In the computer 110, in order to simulate the function of the LSI, a clock counter variable corresponding to a high-speed clock and a frequency division counter variable for realizing a simulation of the low-speed function are prepared.

  In FIG. 3, first, a high-speed function simulation 111 is executed, and it is determined in step 301 whether or not the frequency division counter variable has reached a frequency division period for processing the low-speed function simulation 112. When the determination result is true (having reached the frequency dividing period), the low speed function simulation 112 is executed, and when the condition is false, the low speed function simulation 112 is not processed.

  Next, in step 303, it is determined whether the data synchronization condition is satisfied. If the determination result is true, data synchronization processing with the computer 120 is performed in step 304, and if the determination result is false, data synchronization processing is not performed.

Next, after incrementing the frequency division counter variable and the clock counter variable in steps 306 and 302, it is determined in step 305 whether or not an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 111. The computer 120 executes similar processing to perform parallel simulation of LSI functions.
JP-A-10-91667

  In general, a problem in parallel simulation of LSI functions is that the parallelization method affects the simulation speed. In the above-described conventional method, it is necessary to determine the division condition and increment the division counter variable for low-speed processing simulation. If the frequency ratio between multiple clocks used in the LSI is large, the LSI There is a problem that the speed improvement effect of the parallel simulation of the function is reduced by the simulation of the frequency division process.

  The present invention solves the above-described conventional problem, and avoids a decrease in simulation speed due to processing for absorbing a frequency difference between a plurality of clocks when performing parallel simulation of an LSI function having a clock having a plurality of frequencies. An object of the present invention is to provide a parallel simulation apparatus and a parallel simulation method.

  The parallel simulation apparatus of the present invention is an asynchronous repetitive parallel simulation apparatus that performs parallel simulation of an LSI function having a clock having a plurality of frequencies, and a simulation unit that simulates in parallel the LSI function divided for each frequency of the clock; Data synchronization processing means for executing data synchronization processing between simulations operating in parallel.

  According to the above configuration, by dividing the LSI function for each clock frequency and performing the simulation in parallel, the processing related to the frequency dividing period for absorbing the difference in the clock frequency becomes unnecessary, resulting in the processing. The entire simulation speed can be improved without causing a decrease in the simulation speed.

  The data synchronization processing means determines a change in a specific simulation target signal as a data synchronization condition.

  According to the above configuration, since a data synchronization process is performed by detecting a change in a specific simulation target signal, a data synchronization condition suitable for LSI function simulation is facilitated.

  The data synchronization processing means determines a change in a specific external input signal as a data synchronization condition.

  According to the above configuration, since data synchronization of parallel simulation can be controlled from the outside, various parallel simulations can be executed.

  The data synchronization processing means synchronizes all data at once during data synchronization.

  According to the above configuration, all data can be synchronized at the same time during data synchronization. For example, when it is difficult to extract data synchronization conditions, functional blocks are arranged in parallel without considering it. And the adaptability of parallel simulation can be increased.

  The data synchronization processing means performs synchronization processing only for data that needs to be synchronized during data synchronization.

  According to the above configuration, since only the data that needs to be synchronized at the time of data synchronization can be synchronized, the amount of transferred data at the time of data synchronization can be reduced to the minimum, and the speed of parallel simulation can be improved. Can do.

  The data synchronization processing means performs synchronization processing according to data synchronization conditions specified in advance by file input or the like.

  According to the above configuration, since the data synchronization condition can be designated in advance by file input or the like, it is possible to optimally set the data synchronization condition and the process associated therewith, and the parallel simulation speed can be improved.

  The data synchronization processing means executes the data synchronization processing via a network stretched between means for executing simulation in parallel.

  According to the above configuration, since a computer, a hardware emulator, and the like, which are means for executing simulation in parallel, are connected via a network, a more flexible system configuration can be taken.

  The data synchronization processing means executes the data synchronization processing via a bus connecting between means for executing simulations in parallel.

  According to the above configuration, since the parallel simulation method can be executed by a single computer having a plurality of CPUs connected by a bus as compared with a parallel simulation device configured by network connection, the parallel simulation device that operates at higher speed. Can be realized.

  Furthermore, by incorporating this parallel simulation device into a network-connected parallel simulation system, it becomes possible to configure a wider variety of parallel simulations, and to realize a parallel simulation device capable of high-speed simulation with increased parallelism.

  The parallel simulation method of the present invention is an asynchronous iterative parallel simulation method for parallel-simulating LSI functions having clocks having a plurality of frequencies, wherein the LSI functions are divided for each frequency of the clock, and the divided LSI functions are The simulation is performed in parallel, and data synchronization processing between the simulations operating in parallel is executed.

  According to the above configuration, by dividing the LSI function for each clock and performing the simulation in parallel, the processing related to the frequency dividing period for absorbing the difference in the clock frequency becomes unnecessary, and the simulation resulting from the processing The overall simulation speed can be improved without causing a decrease in speed.

  The data synchronization process is executed by determining a change in a specific simulation target signal as a data synchronization condition.

  According to the above configuration, since the data synchronization process is performed by detecting a change in a specific simulation target signal, a data synchronization condition suitable for a specific LSI function simulation is facilitated.

  The data synchronization process is executed by determining a change in a specific external input signal as a data synchronization condition.

  According to the above configuration, since data synchronization of parallel simulation can be controlled from the outside, various parallel simulations can be executed.

  The data synchronization process is performed on all data at once during data synchronization.

  According to the above configuration, all data can be synchronized at the same time during data synchronization. For example, when it is difficult to extract data synchronization conditions, functional blocks are arranged in parallel without considering it. And the adaptability of parallel simulation can be increased.

  The data synchronization process is performed only for data that needs to be synchronized during data synchronization.

  According to the above configuration, since only the data that needs to be synchronized at the time of data synchronization can be synchronized, the amount of transferred data at the time of data synchronization can be reduced to the minimum, and the speed of parallel simulation can be improved. Can do.

  The data synchronization processing is performed under data synchronization conditions designated in advance by file input or the like.

  According to the above configuration, since the data synchronization condition can be designated in advance by file input or the like, it is possible to optimally set the data synchronization condition and the process associated therewith, and the parallel simulation speed can be improved.

  According to the present invention, in a parallel simulation of an LSI function having a plurality of clocks, the LSI function is divided for each clock and the simulation is performed in parallel, whereby the processing related to the frequency dividing period for absorbing the difference in clock frequency. Therefore, the simulation speed is not reduced due to the processing. The greater the ratio between the multiple clock frequencies, the greater the effect, and the excellent effect that the simulation speed can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and a part of the description of the same parts is partially omitted.

(Embodiment 1)
The first aspect of the present invention is to perform a simulation for each clock frequency in an asynchronous repetitive parallel simulation for simulating an LSI function having a clock having a plurality of frequencies.

  FIG. 2 is a block diagram showing the configuration of the parallel simulation apparatus according to Embodiment 1 of the present invention. In FIG. 2, the parallel simulation apparatus 200 includes a computer 110 and a computer 120 that share the simulation of internal functions of the LSI, and a network 130 that connects them.

  The computer 110 executes a high-speed function simulation 111 that operates with a high-speed clock and a high-speed function simulation 121 that also operates with a high-speed clock. On the other hand, the computer 120 executes a low-speed function simulation 112 that operates with a low-speed clock and a low-speed function simulation 122 that also operates with a low-speed clock.

  The computer 110 and the computer 120 exchange information via the network 130 to realize parallel simulation of LSI functions. Here, the same components as those in FIG. 1 of the conventional method are denoted by the same reference numerals.

  FIG. 4 is a flowchart of the LSI function parallel simulation method according to this embodiment. In the flowchart of FIG. 4, the simulations shown in FIG. 2 are assigned the same reference numerals to indicate that the processing contents are the same.

  A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  First, the flow of simulation processed by the computer 110 will be described. First, a high-speed function simulation 111 and a high-speed function simulation 121 are executed.

  After incrementing the clock counter variable in step 402, it is determined in step 403 whether the data synchronization condition is satisfied. If the determination result is true, the data synchronization process with the computer 120 is performed in step 404, and if the determination result is false, the data synchronization process is not performed.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 111.

  Next, the flow of simulation processed by the computer 120 will be described. First, a low speed function simulation 112 and a low speed function simulation 122 are executed.

  After incrementing the clock counter variable in step 412, it is determined in step 413 whether the data synchronization condition is satisfied. If the determination result is true, data synchronization processing with the computer 120 is performed in step 414, and if the determination result is false, data synchronization processing is not performed.

  Next, in step 415, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 112.

  Further, the above description is supplemented by showing a specific clock frequency. FIG. 5 and FIG. 6 correspond to FIG. 1 and FIG. 2, respectively, and are block diagrams showing the configuration of the parallel simulation apparatus according to the conventional method and this embodiment. It is assumed that the LSI operates with two clocks of 10 MHz and 10 kHz, and there are two functional blocks that operate at the respective clock frequencies.

  In FIG. 5, in the parallel simulation apparatus 500 of the conventional method, a computer 110 executes a function simulation 511 operating at 10 MHz and a function simulation 512 operating at 10 kHz, and operates at a function simulation 521 and 10 kHz operating at 10 MHz. The computer 120 executes a function simulation 522.

  On the other hand, in FIG. 6, in the parallel simulation apparatus 600 of the present embodiment, a function simulation 511 that operates at 10 MHz and a function simulation 521 that operates at 10 MHz are executed by the computer 110, and the function that operates at 10 kHz. A simulation 512 and a simulation 522 of a function operating at 10 kHz are executed on the computer 120.

  As described above, the LSI function having clocks of a plurality of frequencies is simulated at each clock frequency, and when these simulations are executed in parallel, the frequency division period for absorbing the difference in the clock frequency is affected. No processing is required, and the simulation speed is not lowered due to the processing, and the speed improvement effect of the parallel simulation can be sufficiently obtained.

(Embodiment 2)
The second aspect of the present invention is to determine a change in a specific simulation target signal as a data synchronization condition in the parallel simulation method of the first embodiment. At the time of simulation execution, data synchronization processing between simulations operating in parallel when a specific signal is changed by the simulation is executed.

  FIG. 13 is a flowchart of the parallel simulation method according to the second embodiment of the present invention. The parallel simulation apparatus according to the present embodiment has the configuration shown in FIG. 2 or FIG. 6, and will be described with reference to FIG.

  A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  The computer 110 first executes a high-speed function simulation 511 and a high-speed function simulation 521 that operate at 10 MHz. After incrementing the clock counter variable in step 402, it is determined in step 1303 whether the data synchronization condition is satisfied.

  Here, the data synchronization condition is a change in a specific signal by simulation. In step 1303, it is determined whether or not a specific signal has been changed by simulation. If the determination result is true, data synchronization processing with the computer 120 is performed in step 404, and if the determination result is false, data synchronization processing is performed. Absent.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 511.

  The computer 120 is the same as the processing in the computer 110 except that a low-speed function simulation 512 and a low-speed function simulation 522 that operate at 10 kHz are executed instead of a high-speed function simulation that operates at 10 MHz.

  In this way, by determining a change in a specific signal and setting it as a data synchronization condition, a data synchronization condition suitable for a specific LSI function simulation is facilitated, and an effect of improving the speed of parallel simulation can be obtained. .

(Embodiment 3)
A third aspect of the present invention is to determine a change in a specific external input signal as a data synchronization condition in the parallel simulation method of the first embodiment. During simulation execution, data synchronization processing between simulations operating in parallel when a specific external input signal changes is executed.

  FIG. 9 is a block diagram showing a configuration of a parallel simulation apparatus according to Embodiment 3 of the present invention. In FIG. 9, the parallel simulation apparatus 900 includes a computer 110 and a computer 120 that share the simulation of the internal functions of the LSI, a network that connects the external synchronization processing unit 930, and the external synchronization processing unit 930 and the computers 110 and 120. 910 and 920.

  The computer 110 executes a high-speed function simulation 511 that operates at 10 MHz and a high-speed function simulation 521 that also operates at 10 MHz. On the other hand, the computer 120 executes a low-speed function simulation 512 that operates at 10 kHz and a low-speed function simulation 522 that also operates at 10 kHz.

  The external synchronization processing unit 930 monitors specific external input signals and also monitors the processing of the computer 110 and the computer 120 through the network 910 and the network 920, and controls the exchange of synchronization signals and data.

  FIG. 14 is a flowchart of the parallel simulation method according to the third embodiment of the present invention. A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  The computer 110 first executes a high-speed function simulation 511 and a high-speed function simulation 521 that operate at 10 MHz. After incrementing the clock counter variable in step 402, it is determined in step 1403 whether the data synchronization condition is satisfied.

  Here, the data synchronization condition is a change in a specific external input signal. In step 1403, it is determined whether or not a specific external input signal has changed. If the determination result is true, data synchronization processing with the computer 120 is performed in step 404, and if the determination result is false, data synchronization processing is performed. Absent.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 511.

  The computer 120 is the same as the processing in the computer 110 except that a low-speed function simulation 512 and a low-speed function simulation 522 that operate at 10 kHz are executed instead of a high-speed function simulation that operates at 10 MHz.

  As described above, by determining a change in a specific external input signal and setting it as a data synchronization condition, it is possible to control the data synchronization of the parallel simulation from the outside, so that various parallel simulations can be executed.

(Embodiment 4)
According to a fourth aspect of the present invention, in the parallel simulation methods of the first to fourth embodiments, all data is synchronized at a time during data synchronization.

  FIG. 15 is a flowchart of the parallel simulation method according to the fourth embodiment of the present invention. The parallel simulation apparatus according to the present embodiment has the configuration shown in FIG. 2 or FIG. 6, and will be described with reference to FIG.

  A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  The computer 110 first executes a high-speed function simulation 511 and a high-speed function simulation 521 that operate at 10 MHz.

  After incrementing the clock counter variable in step 402, it is determined in step 403 whether the data synchronization condition is satisfied. If the determination result is true, data synchronization processing with the computer 120 is performed in step 1504. At that time, all data is synchronized at once. If the determination result is false, data synchronization processing is not performed.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 511.

  The computer 120 is the same as the processing in the computer 110 except that a low-speed function simulation 512 and a low-speed function simulation 522 that operate at 10 kHz are executed instead of a high-speed function simulation that operates at 10 MHz.

  In this way, by performing synchronization processing of all data at the time of data synchronization, for example, when extraction of data synchronization conditions is difficult, it becomes possible to arrange functional blocks in parallel without considering it, The adaptability of parallel simulation can be increased.

(Embodiment 5)
According to a fifth aspect of the present invention, in the parallel simulation methods of the first to fourth embodiments, synchronization processing is performed only for data that needs to be synchronized during data synchronization.

  FIG. 16 is a flowchart of the parallel simulation method according to the fifth embodiment of the present invention. The parallel simulation apparatus according to the present embodiment has the configuration shown in FIG. 2 or FIG. 6, and will be described with reference to FIG.

  A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  The computer 110 first executes a high-speed function simulation 511 and a high-speed function simulation 521 that operate at 10 MHz.

  After incrementing the clock counter variable in step 402, it is determined in step 403 whether the data synchronization condition is satisfied. If the determination result is true, in step 1604, data synchronization processing with the computer 120 is performed. At that time, synchronization processing is performed only for data that needs to be synchronized. If the determination result is false, data synchronization processing is not performed.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 511.

  The computer 120 is the same as the processing in the computer 110 except that a low-speed function simulation 512 and a low-speed function simulation 522 that operate at 10 kHz are executed instead of a high-speed function simulation that operates at 10 MHz.

  In this way, by performing synchronization processing only on data that needs to be synchronized during data synchronization, the amount of transferred data during data synchronization can be reduced to a minimum, and an effect of improving the speed of parallel simulation can be obtained. Note that selection of data that needs to be synchronized includes a method that is designated in advance and a method that is dynamically determined at the time of execution.

(Embodiment 6)
According to a sixth aspect of the present invention, in the parallel simulation methods of the first to fourth embodiments, the data synchronization condition is designated in advance by file input or the like.

  FIG. 10 is a flowchart of the parallel simulation method according to the sixth embodiment of the present invention. The parallel simulation apparatus according to the present embodiment has the configuration shown in FIG. 2 or 6 and will be described with reference to FIG.

  A clock counter variable corresponding to a clock is prepared for each of the computer 110 and the computer 120 in order to simulate the function of the LSI.

  In the computer 110, first, in step 1001, a file for designating data synchronization conditions is read. FIG. 11 is a diagram illustrating a configuration example of a file for designating data synchronization conditions. In this embodiment, for each function 1101 to be simulated, a synchronization condition 1102 and data 1103 for performing synchronization processing are designated.

  Next, the computer 110 executes a high-speed function simulation 111 and a high-speed function simulation 121.

  After incrementing the clock counter variable in step 402, in step 403, a condition is determined based on the data synchronization condition read in step 1001. If the determination result is true, the data synchronization process with the computer 120 is performed in step 404, and if the determination result is false, the data synchronization process is not performed.

  Next, in step 405, it is determined whether an end condition has been reached. If the determination result is true, the simulation is terminated. If the determination result is false, the process returns to step 111.

  In the computer 120, a file for designating data synchronization conditions is first read in step 1011. A low-speed function simulation 112 and a low-speed function simulation that operate with a low-speed clock are used instead of a high-speed function simulation that operates with a high-speed clock. The processing is the same as the processing in the computer 110 except that 122 is executed.

  As described above, by designating the data synchronization condition in advance by file input or the like, it is possible to optimally set the data synchronization condition and the processing associated therewith, and an effect of improving the speed of parallel simulation can be obtained.

(Embodiment 7)
FIG. 7 is a block diagram showing a configuration of a parallel simulation apparatus according to Embodiment 7 of the present invention. In FIG. 7, the parallel simulation apparatus 700 includes a single computer 701, and the computer 701 includes a CPU 710 and a CPU 720 that share the simulation of the internal functions of the LSI, and a bus 730 that connects them.

  The CPU 710 executes a simulation 511 and a simulation 521 of a function operating with a high-speed clock, and the CPU 720 executes a simulation 512 and a simulation 522 of a function operating with a low-speed clock.

  7 is compared with FIG. 6, the CPU 710 corresponds to the computer 110, the CPU 720 corresponds to the computer 120, and the bus 730 corresponds to the network 130.

  By configuring the parallel simulation apparatus in this way, each of the above-described embodiments can be performed by one computer including two CPUs connected by a bus compared to a parallel simulation apparatus configured by two computers connected by a network. Therefore, a parallel simulation apparatus that operates at high speed can be realized.

(Embodiment 8)
FIG. 8 is a block diagram showing a configuration of a parallel simulation apparatus according to Embodiment 8 of the present invention. In FIG. 8, a parallel simulation apparatus 800 includes a hardware emulator 810 and a computer 120 that share the simulation of the internal functions of the LSI, and a network 130 that connects them.

  The hardware emulator 810 executes a simulation 511 and a simulation 521 of a function operating at 10 MHz, and further executes a simulation 811 of a function operating at 100 MHz. The computer 120 executes a simulation 512 and a simulation 522 of a function operating at 10 kHz.

  When FIG. 7 is compared with FIG. 6, since the hardware emulator 810 is employed instead of the computer 110, the computer 110 operates at 100 MHz in addition to the simulation 511 and the simulation 521 of the function that operates at 10 MHz. The function simulation 811 can be processed.

  In this way, by configuring a parallel simulation device using a hardware emulator, a parallel simulation device capable of executing a simulation at a higher speed than a parallel simulation device configured with the same computer is realized. Can do.

(Embodiment 9)
FIG. 12 is a block diagram showing a configuration of a parallel simulation apparatus according to Embodiment 9 of the present invention. In FIG. 9, the parallel simulation apparatus 1200 includes a computer 701 of the parallel simulation apparatus according to the seventh embodiment, computers 1210 and 1220, and a network 130 that connects them.

  The computer 701 executes a simulation 511 and a simulation 521 of a function operating at 10 MHz, and a simulation 512 and a simulation 522 of a function operating at 10 kHz.

  The computer 1210 executes a simulation 1211 of a function operating at a high speed of 100 MHz, and the computer 1220 executes a simulation 1221 and a simulation 1222 of a function operating at a low speed of 32 kHz.

  In this way, by configuring a complex parallel simulation device, it is possible to configure a wider variety of parallel simulations compared to a parallel simulation device configured with the same computer, enabling high-speed simulation with increased parallelism. A parallel simulation apparatus can be realized.

  The parallel simulation apparatus and parallel simulation method of the present invention absorbs differences in clock frequencies by performing parallel simulation by dividing LSI functions for each clock frequency in parallel simulation of LSI functions having a plurality of clocks. The parallel simulation apparatus for performing parallel simulation of LSI functions having clocks of a plurality of frequencies has the effect of eliminating a decrease in the simulation speed due to the processing because the processing related to the frequency division cycle is unnecessary It is also useful as a parallel simulation method.

The block diagram which shows embodiment of the parallel simulation apparatus by a conventional method. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 1 of this invention. The flowchart of the parallel simulation by a conventional method. The flowchart which shows the parallel simulation method which concerns on Embodiment 1 of this invention. The block diagram which shows embodiment of the parallel simulation apparatus by a conventional method. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 7 of this invention. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 8 of this invention. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 3 of this invention. The flowchart which shows the parallel simulation method which concerns on Embodiment 6 of this invention. The figure which shows the structural example of the file which designates a data synchronization condition. The block diagram which shows the structure of the parallel simulation apparatus which concerns on Embodiment 9 of this invention. The flowchart which shows the parallel simulation method which concerns on Embodiment 2 of this invention. The flowchart which shows the parallel simulation method which concerns on Embodiment 3 of this invention. The flowchart which shows the parallel simulation method which concerns on Embodiment 4 of this invention. The flowchart which shows the parallel simulation method which concerns on Embodiment 5 of this invention.

Explanation of symbols

100, 200, 500, 600, 700, 800, 900, 1200 Parallel simulation apparatus 110, 120, 701, 1210, 1220 Computer 111, 121 High-speed function simulation 112, 122 Low-speed function simulation 130, 910, 920 Network 301- 306, 311 to 316, 402 to 405, 412 to 415, 1001, 1011, 1303, 1313, 1403, 1413, 1504, 1514, 1604, 1614 Step 511, 521 Simulation of function operating at 10 MHz 512, 522 Operating at 10 kHz Of function to perform 710, 720 CPU
730 Bus 810 Hardware emulator 811, 1211 Simulation of function operating at 100 MHz 930 External synchronization processing unit Step 1101 Function to simulate 1102 Synchronization condition 1103 Data to perform synchronization processing 1221, 1222 Simulation of function operating at 32 kHz

Claims (2)

An asynchronous repetitive parallel simulation device for parallel simulation of LSI functions having clocks of multiple frequencies,
Simulation means for simulating in parallel LSI functions divided for each frequency of the clock;
Data synchronization processing means for executing data synchronization processing between simulations operating in parallel ,
The data synchronization processing means, parallel simulation device you determine a change in the specific external input signals as data synchronization condition. An asynchronous iterative parallel simulation method for parallel simulation of LSI functions having clocks of multiple frequencies,
Dividing the LSI function for each clock frequency, simulating the divided LSI functions in parallel,
A parallel simulation method for performing data synchronization processing between simulations operating in parallel by determining a change in a specific external input signal as a data synchronization condition .

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