JP2000348076A - Method and device for simulation and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable verification in detailed timing while holding a simulation speed almost at an algorithm level by detailing the range of a specific test pattern and a specific part of an object to be verified into a lower verification level. SOLUTION: An algorithm simulator 7 inputs a test pattern 5 and design data 1 of the top verification level and verification of the top level is performed for the whole circuit, and the simulation result is outputted and held as an algorithm simulation result 8. A delay information extracting means 9 analyzes the structure of the verification object and provides delay values obtained in time-series units of individual verification levels in all combinations of condition decision making from inputs of the respective verification levels to respective signals and delay information 10 for finding them. A simulation result detailing means 11 details the simulation result on the basis of the delay information 10 in time-series units of the verification levels for detailing the time series of simulation result while using the detailing parameters of the verification of detailing control data 6 as conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system circuit design, and more particularly, to a system circuit design using a large-scale circuit simulation.

[0002]

2. Description of the Related Art Conventionally, system circuit design has proceeded from specifications to algorithms, behaviors, register transfer (RT), and logic circuits, and verification has been performed on these descriptions or on a netlist or database. .

FIG. 16 shows a design level of a system circuit and a data time series of each verification. As shown in FIG.
These four levels of design data are verified as the design progresses. At the level of the uppermost algorithm in the left column of FIG. 16, it is confirmed that the operation matches the specification. At this stage, there is no distinction between hardware and software, and data flow verification is mainly performed. The unit of the time series of the verification follows the data flow.

[0004] Next, at the second-stage behavior level in the left column of FIG. 16, the operation of hardware is mainly verified. Here, the data flow is analyzed in the same manner as the algorithm, but verification is performed in consideration of more detailed timing. Verification in consideration of more detailed timing is, for example, verification of data input / output in units of hardware control states.

Further, at the level of the register transfer at the third stage in the left column of FIG. 16, verification is performed on a circuit configuration composed of a register and an arithmetic unit, which is behaviorally synthesized or manually designed from the above algorithm and behavior. Here, the register is a latch, a flip-flop, or the like, and the arithmetic unit is a multiplier, a selector, a counter, or the like. In the case of a general synchronous circuit, the timing of data input / output to be verified depends on a clock input to a register. Therefore, the verification timing is performed in units of a clock cycle (clock cycle).

Finally, at the level of the fourth stage logic circuit in the left column of FIG. 16, logic synthesis or manual design is performed.
Verification of a circuit configuration including a register and a combinational circuit is performed. The circuit configuration here is a circuit configuration including a gate circuit such as a logical product and an inverter. The same time as the real world (in units of nanoseconds (ns), microseconds (μs), etc.) is used as the time series unit for verification.

[0007] With the increase in the scale of digital systems to be designed, the circuit scale and test patterns at the time of verification have increased, and the verification time has become a bottleneck. Simulation techniques for system circuits include simulation, emulation, static timing analysis, and formal verification.

Simulation and emulation are:
A test pattern (circuit input data) to be given to a circuit and an expected value of the circuit output or a signal inside the circuit are prepared, and the test pattern is given to software or an apparatus for imitating a circuit of the present design level, and the imitated circuit output or This is a method for verifying whether a signal inside the circuit matches an expected value. Generally, when circuit imitation is performed by software of a computer, it is called a simulation, and when the designed circuit is imitated by a circuit mounting device, it is called emulation. Static timing analysis is a technique for analyzing whether a synchronous logic circuit operates with desired performance without using a test pattern. Formal verification is a method of comparing two designed circuits logically or functionally and verifying that they are equivalent circuits. Static timing analysis and formal verification have the advantage that the entire circuit can be verified at high speed.However, since the circuit to be verified is limited to a logic circuit or a register transfer circuit that can be synthesized, the design process is limited It cannot be verified without progress. The following describes a conventional simulation (and emulation) technique.

Conventional techniques for reducing the simulation time include a method of reducing the number of events, a method of increasing the simulation speed itself, a multi-level mixed simulation, and a method of refining a specific verification time range.

As a conventional simulation technique for reducing the number of events, there is a cycle-based simulation. The current mainstream circuit simulator is called an event-driven simulator, which is a method of executing a processing portion having a variable at which an event has occurred (the signal of the circuit has changed). As the size of the verification target increases and the event list monitored by the simulator increases, the simulation speed decreases. In contrast, the cycle-based simulation can increase the simulation speed by monitoring events only when the clock changes, instead of monitoring events at all times.

As a conventional technique for increasing the simulation speed, there is a technique for reducing the load on a simulator such as a hardware accelerator and parallel / distributed simulation. The hardware accelerator is a method in which a part or the whole of a simulation is performed by hardware dedicated to the simulation. In parallel / distributed simulation, a circuit to be verified is divided, and a plurality of processors communicate with each other to reduce the load on the simulation of each processor.

The multi-level mixed simulation is a simulation method in which a plurality of verification targets are verified by different simulator engines. Data communication is performed between the verification targets via the determined interface. For example, only a specific circuit can be verified at the register transfer level, and the rest can be verified at a high abstraction level such as a behavior or an algorithm.

Japanese Patent Application Laid-Open No. Hei 10-261002 describes a method and means for refining the time in a certain time range for register transfer or logic circuit simulation by switching between different hardware models or simulators. Thereby, the timing can be refined for a specific test pattern for a specific verification time, and the other test patterns and other verification times can be simulated at high speed, so that the total simulation can be speeded up.

[0014]

However, according to the above-described prior art of simulation, it is not possible to simulate a system having a large number of test patterns and a circuit scale at high speed with detailed behavior, register transfer level and gate level.

[0015] The cycle-based simulator
It is about 10 to 100 times faster than a driven simulator, but not fast enough to be applied to a large-scale system circuit. Generally, the verification levels at which the cycle-based simulation can be performed are only the register transfer level and the gate level. Further, the hardware accelerator, the distributed simulation, and the multi-level mixed simulation have communication overhead between processors or processes, and the actual simulation speed depends on the module that simulates the verification object having the highest load. Therefore, if the verification level of a module that processes a large amount of test patterns such as image processing at high speed is reduced and the simulation is performed, the verification speed is reduced. For this reason, a detailed simulation cannot be performed for the entire system. Japanese Patent Application Laid-Open No. H10-261002 describes a method of switching between different hardware levels or simulators for a certain period of time.

In this method, since the time unit to be verified is a unit of real time (ns, μs, etc.), it cannot be used if it does not always match an algorithm or a time series such as a behavior level. For example, a data time series in a behavior is determined in units of states (super states), but the states are merged (divided) during behavioral synthesis.
And the state does not always match the operation of the clock. In this method, the simulation of the entire system must be started from the register transfer level, and cannot be applied to the algorithm and the behavior like the cycle-based simulator.

An object of the present invention is to provide a high-speed simulation method, apparatus, and recording method for refining only a part of an object to be verified to an arbitrary verification level based on a simulation result in overall verification, which could not be performed by the above-described conventional technology. Is to provide a medium.

[0018]

A simulation method according to the present invention is a simulation method for verifying a circuit module, and performs a simulation at the highest verification level in the whole verification target and the whole simulation time series. And refining a specific test pattern range and a specific part of the verification target to a specific lower verification level from the result of the simulation at the highest verification level, Objective is achieved.

In the step of refining, the structure of the object to be verified at a specific verification level is analyzed, and the input timing of the object to be verified is detailed in a time-series unit of the specific verification level, so that only a specific part The verification level of the simulation may be refined.

A simulation apparatus according to the present invention is a simulation apparatus for verifying a circuit module, comprising: first input means for inputting a structure and a simulation pattern to be verified at a plurality of levels; Second input means for inputting a portion and a range of a verification time series; top-level simulation means for simulating the entire verification target at the highest verification level; and data input / output timing of the verification target at a specific verification level. There are provided timing extracting means for extracting, and time series refinement means for partially refining simulation input / output timing down to the time series unit at the verification level, thereby achieving the above object.

The timing extracting means may include an analyzing means for analyzing a structure to be verified at a specific verification level, and a calculating means for calculating all input / output and input / output timing of a specific partial system.

The time series refinement means includes a conversion means for rearranging the time series of the simulation result based on the simulation result in the overall verification and the input / output timing of the refined portion, and converting the result into a more detailed input / output time series. May have.

A recording medium according to the present invention is a recording medium in which a program for causing a computer to execute a simulation method for verifying a circuit module is recorded, wherein the simulation method includes a whole verification object and a whole simulation time series. Performing the simulation of the highest verification level in the range, and, based on the result of the simulation of the highest verification level, detailing the specific test pattern range and the specific portion to be verified to a specific lower verification level. And the above-mentioned object is achieved.

The operation will be described below.

According to the present invention, since only a part of the test object and a part of the test pattern are detailed, the detailed simulation is retried while maintaining the simulation speed of the entire object to be verified substantially equal to the algorithm level. The simulation of the entire system can be performed at high speed without any problem.

When the verification level is lowered, the simulation can be performed in detail, but the speed becomes extremely low. Therefore, considering the whole system, only a part of the specific part is simulated at a low level, and it can be determined whether the specific part is simulated at a low speed or a high speed at which level. That is, the simulation is performed at a level corresponding to that part.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a simulation apparatus 1 according to the present invention.
00 is shown.

The simulation apparatus 100 shown in FIG.
Receives circuit design data 1-4, test pattern 5, and refinement control data 6, and outputs refinement simulation result 12. The simulation device 100 includes an algorithm simulator 7, delay information extracting means 9,
Simulation result refinement means 11.
Further, the simulation device 100 holds an algorithm simulation result 8 output by the algorithm simulator 7 and delay information 10 output by the delay information extracting means 9.

The test pattern 5 is a test pattern for simulation. In this case, the test pattern at the highest verification level is provided by a designer, another device, or software. The test pattern is, for example, image data, audio data, or the like. The circuit design data 1 to 4 represent design data to be verified. FIG. 1 shows, as examples of circuit design data, an algorithm description (1) using a high-level language program, a behavior description (2) using a state transition diagram, a register transfer circuit description (3) using a hardware description language, and a logic circuit description (4). )It is shown. The refinement control data 6 is data that is provided by a designer or another device or software and indicates a site to be verified to be refined, a time series range thereof, and a level to be refined.

The algorithm simulator 7 receives the test pattern 5 and the design data 1 at the highest verification level as input, performs the highest level verification on the entire circuit, and outputs a simulation result as an algorithm simulation result 8. And hold.

The delay information extracting means 9 analyzes the structure of the object to be verified, and combines all the condition determinations from input to each signal at each verification level (= all control states).
, A delay value obtained in a time-series unit (step, state, clock cycle, nanosecond (ns), etc.) of each verification level or delay information 10 for obtaining the same is provided. The simulation result refinement means 11 sets a verification level for refining the time series of the simulation result on the condition of the refinement parameters (verification level, site to be verified, range of the verification time series) of the verification of the refinement control data 6. The simulation result is refined based on the delay information 10 in a time-series unit. The detailed result of the simulation of the constituent means 11 is the detailed simulation result 1
2 and saved.

Hereinafter, as an embodiment of the present invention, a detailed simulation from an algorithm to a behavior and a gate level (logic circuit) for only a part of the time series to be verified will be described. Here, as a verification target example, a counter circuit that counts the number of times the same value is continuously input will be described.

FIG. 2 shows a configuration example of the whole circuit to be verified. In the circuit shown in FIG. 2, test bench data A and B are transmitted through a delay circuit (Delay 1) to ena.
ble, and input as data. The verification target to be detailed is Sample, and the input of Sample is enable and data, and the output is count. The input rate per data of the test bench is set to 1 data / state at the behavior level and 1 data / clock at the register transfer level. D
elay1 is a one-clock or one-state delay circuit. Assume that a clock cycle of 100 ns is given.

FIG. 3 shows an example in which the Sample part of FIG. 2 is described in C language. FIG. 4 shows a state transition diagram of the Sample portion of FIG. 2, FIG. 5 shows a register transfer circuit, and FIG. 6 shows a gate circuit diagram. Hereinafter, S in FIG.
The processing of the circuit of the sample part will be described with reference to FIG.

The first line of FIG. 3 shows a function name sample and input / output names enable, data, and count. "enable" is an input variable indicating the start of input of data.
As shown in the −11th line, the output is initialized as count = −1. "indata" represents input data. coun
t is output data, and if enable = 0, inda
If the value of ta is the same continuously, the number is output.
If it is not continuous, 0 is output. Lines 2-4 are enab
This is a variable declaration of le, data, and count.
Lines 6 and 7 are declarations of variables used only inside this circuit. Here, previo that saves the data
us_data and a mode in which the result of the continuous determination is stored are declared. The 9th to 12th lines are set such that count = −1 and mode = INIT in the process when enable = 1. Lines 13-24 represent the process of enable $ 1. 1
The third line determines whether or not data = previous_data, that is, whether or not data is continuously input. If the data is continuous, process lines 15-20, otherwise process lines 22 and 23. In the fifteenth line, mode = CON
T, that is, whether or not data is already continuous with the immediately preceding data is determined. If the judgment is true, cou
The nt value is increased by one (line 16). If false, cou
It is assumed that nt = 1 (line 18). The 20th line indicates that continuous data has been read.
NUED).

Lines 22-23 are processing for reading non-consecutive data, in which "count" is set to "0", and "NONC (-ONTINUED)" indicating non-consecutive data is substituted for "mode". Finally, save the currently read data.

Hereinafter, the simulation processing of the present invention will be described using the above circuit as an example.

STEP 1: Input of Verification Circuit (FIGS. 1, Inputs 2 and 6) sample is input as a verification target to be detailed, and algorithm level 1-15 steps are input as a time series range (here, the algorithm time series is used). The unit is called a step).

It is assumed that the verification level is given one of behavior, register transfer, and logic when a simulation is actually performed.

STEP 2: Simulation at the highest level (FIG. 1, algorithm simulator 7) FIG. 7 shows a simulation example of the above algorithm. The algorithm is the highest level in the simulation processing of the present invention. In FIG. 7, at the first step, initialization is performed with enable = 1. In the second and subsequent steps, the number of continuous data is output each time input data is given.

STEP 3: Refinement of delay to be verified (FIG. 1, delay information extracting means 9, simulation result refining means 11) The case of the behavior level and the case of the register transfer level and the gate level will be described separately.

(In the case of the behavior level) FIG.
Is represented by a state transition diagram as a behavior model. State 0 is the initializing state and enabl
When e = 1, count = −1 is output. State 1 is a state in which the first continuous data (data) is read and c
output = 1 is output. State 2 is a state in which two or more pieces of continuous data (indata) are read and count is 1
One. State 3 is for non-continuous data (indat
While reading a), count = 0 is output.
These four states are described in the algorithm description 9, 13, 1
It can be determined by the condition determination formula on the fifth line. By recording these condition determination values each time the algorithm simulator 7 executes the condition determination, a history of the condition determination shown in FIG. 8 is obtained. Also, input data indat in the state diagram
The number of necessary state transitions from the reading of a until the output count is obtained is all ones. So, coun
The output result is changed as shown in FIG. 9 in which t is delayed by one compared to FIG.

(Register transfer level)
FIG. 10 shows a register obtained by synthesizing the above-described algorithm.
4 shows a simulation result of a transfer circuit. Because of the register transfer, the unit of the time series is a clock cycle.

FIG. 11 shows an example of analyzing the structure of the input / output path of the register transfer circuit of FIG. From the data path structure of the register transfer circuit in FIG. 11, the minimum value of the number of flip-flop stages is obtained by solving the minimum path search problem of the path from input enable, data to output count. In this example, ena
It can be seen that there are two flip-flops (flip-flops 1 and 2 in FIG. 11) between ble → count and between data → count. Accordingly, the output data “comun” from the input data “indata” and “enable”
The delay of t is obtained as 2 clocks, and a simulation result of register transfer is obtained.

(In the case of a gate-level logic circuit) FIG.
7 shows an example of a simulation result at the gate level with respect to the input of FIG. To obtain the simulation result of the gate-level logic circuit shown in FIG. 12, the delay of the flip-flop circuit and the wiring from the flip-flop 2 to the output count shown in FIG. It is preferable to add a delay to the signal count. However, the input signals enable, inda
ta is an input delay to the sample, so
Determined in TEP4.

STEP 4: Calculation of input delay to detail target (FIG. 1, delay information extracting means 9, simulation result detailing means 11) In STEP 4, similar to STEP 3, the verification target refined from the test pattern input Find the delay (number of states, number of clocks) until input to. Here, ena
ble and indata are obtained. Here, FIG.
In the behavior 1 and the register transfer, one state and one clock delay are added by delay1 shown in FIG. In a gate-level logic circuit, indata, e
An output delay of delay1 in FIG. 2 and a wiring delay are added to the input signal of the enable signal.

STEP 5: Mixed display of simulation results (FIG. 1, simulation result detailing means 11) FIG. 13 is a diagram showing an example in which the algorithm of FIG. 7 and the behavior simulation of FIG. 9 are simultaneously displayed.

As shown in FIG. 13, in the range to be detailed, the time is displayed in a time series in which the verification level is lowered, and in the other range, the time is displayed in the time series of the highest verification level. Testbench A and B in FIG. 13 show test bench inputs,
The algorithm step represents a time-series number using data input / output as one unit. The step of the behavior in FIG. 13 represents the number of the state transition. The range of steps to be refined here is from 1 to 15. No other status is displayed. The count has a one-state delay at the output of the sample. In FIG. 13, the numbers 0, 1, 2, and 3 in the rows representing the states represent the states 0, 1, 2, and 3 in FIG.

FIG. 14 shows an example in which the algorithm of FIG. 7 and the simulation of the register transfer of FIG. 10 are simultaneously shown. Also in the register transfer waveform display of FIG. 14, 1 to 15 steps are displayed by a clock waveform similarly to the behavior. In other cases, a time-series display of data input / output of the algorithm is performed.

FIG. 15 shows an example in which the algorithm of FIG. 7 and the simulation of the gate-level logic circuit of FIG. 11 are simultaneously shown. In the waveform display of the gate-level logic circuit shown in FIG. 15, the steps from 1 to 15 are expressed in time (ns)
The waveform is displayed as follows.

It is possible to provide a recording medium on which a program for causing a computer to execute a simulation method for verifying a circuit module is recorded. The simulation method includes a step of performing the simulation of the highest verification level in the entire verification target and the entire simulation time series, and a result of the simulation of the highest verification level, the range of the specific test pattern. And a step of refining a specific portion to be verified to a specific lower verification level. Further, in the step of refining, the structure of the verification target at a specific verification level is analyzed, and the input timing of the verification target is refined in a time-series unit of the specific verification level, so that the verification level of the simulation is limited to a specific part. May be refined.

A program for causing a computer to execute a simulation method for verifying a circuit module is recorded on a recording medium in a computer-readable format. By installing the program in a computer, the computer can be operated as a simulation device for verifying a circuit module.

The recording medium for recording the program is not limited to a solid recording medium such as a floppy (registered trademark) disk or CD-ROM. Recording media also includes non-solid media such as carrier waves that carry signals.

[0055]

According to the present invention, the verification of an arbitrary circuit module to be verified can be performed in the range of an arbitrary test pattern in detail. Thus, it is possible to perform verification at a detailed timing while maintaining the simulation speed substantially equal to the algorithm level. Since there is a trade-off between lowering the verification level and speeding up the simulation, select a combination of the overall verification level and the verification level of the specific part according to the simulation request level of the entire system, and perform verification. I can do it.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a simulation device of the present invention.

FIG. 2 is a diagram illustrating a configuration example of an entire verification target;

FIG. 3 shows a sample of FIG.
It is a figure which shows the example described by.

FIG. 4 is a diagram showing an example in which FIG. 3 is represented by a behavior level state transition diagram.

FIG. 5 is a diagram illustrating an example of a register transfer circuit diagram obtained by behaviorally synthesizing the description of FIG. 3;

FIG. 6 is a diagram showing an example of logically synthesizing the logic circuit diagram of FIG. 5;

FIG. 7 is a diagram illustrating an example of an algorithm-level test pattern input and an output sequence to be verified;

8 is a diagram illustrating an example of a sequence of algorithm-level condition determination for the input of FIG. 7;

FIG. 9 is a diagram illustrating an example of a simulation result of a behavior level with respect to the input of FIG. 7;

FIG. 10 is a diagram illustrating an example of a simulation result of a register transfer level with respect to the input of FIG. 7;

11 is a diagram illustrating an example of analyzing the structure of an input / output path of the register transfer circuit of FIG. 5;

12 is a diagram illustrating an example of a simulation result of a gate level with respect to the input of FIG. 7;

13 is a diagram showing an example in which the algorithm of FIG. 7 and the behavior simulation of FIG. 9 are simultaneously displayed.

14 is a diagram showing an example in which the algorithm of FIG. 7 and the simulation of the register transfer of FIG. 10 are simultaneously displayed.

15 is a diagram illustrating an example in which the algorithm of FIG. 7 and the simulation of the gate-level logic circuit of FIG. 12 are simultaneously illustrated.

FIG. 16 is a diagram showing a design level of a system circuit and a data time series of each verification.

[Explanation of symbols]

 1, 2, 3, 4 Circuit design data 5 Test pattern 6 Refinement control data 7 Algorithm simulator 8 Algorithm simulation result 9 Delay information extraction means 10 Delay information 11 Simulation result refinement means 12 Refinement simulation result 100 Simulation device

Claims (6)

[Claims] 1. A simulation method for verifying a circuit module, comprising: performing a simulation at a highest verification level within a range of a whole verification target and a whole simulation time series; A simulation method comprising, based on a result of the simulation, refining a specific test pattern range and a specific portion to be verified to a specific lower verification level. 2. In the step of refining, the structure of the object to be verified at a specific verification level is analyzed, and the input timing of the object to be verified is refined in a time-series unit of the specific verification level, thereby The simulation method according to claim 1, wherein the verification level of the simulation is refined only in a part. 3. A simulation device for verifying a circuit module, comprising: first input means for inputting a structure and a simulation pattern to be verified at a plurality of levels; a verification level to be refined; a verification target portion; and a verification time series. Second input means for inputting a range of the following, highest-level simulation means for simulating the entire verification target at the highest verification level, and timing extraction means for extracting the data input / output timing of the verification target at a specific verification level And a time series refinement means for partially refining simulation input / output timing down to a verification level time series unit. 4. The apparatus according to claim 1, wherein said timing extracting means comprises: analyzing means for analyzing a structure to be verified at a specific verification level; and calculating means for calculating all input / output and input / output timing of a specific partial system. 3. The simulation device according to 3. 5. The time-series refinement means rearranges the time-series of the simulation result from the simulation result in the overall verification and the input / output timing of the refined part,
Having conversion means for converting to a more detailed input / output time series,
The simulation device according to claim 3. 6. A recording medium on which a program for causing a computer to execute a simulation method for verifying a circuit module is recorded, wherein the simulation method has the highest rank in a whole verification target and a whole simulation time series. Performing a simulation of a verification level of the following, and refining a specific test pattern range and a specific portion of the verification target to a specific lower verification level from a result of the simulation of the highest verification level. Recording media, including;