JP3071921B2 - LSI design support equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI design support apparatus capable of simplifying the design of an LSI, particularly, a function design.

[0002]

2. Description of the Related Art In recent years, a function description and a verification based on the function description are often used for designing an LSI. By designing the functions without being conscious of the layout and logic circuit of the LSI, there is an advantage that the completeness of a higher-order system including the LSI can be improved. Therefore, at this level, L
It is desirable to be able to describe / verify separately from the hardware of the SI.

However, this functional description is only a part of the design of the LSI, and eventually becomes an LSI. Therefore, it is inevitably faced with some problem of the LSI hardware someday. Considering only the LSI design aspect, it is desirable that the design be made in consideration of the LSI hardware as soon as possible. In other words, it is desirable that the hardware is designed in consideration of the function description level.

In particular, it is possible to create a logic description by logic synthesis from a function level called RTL (register transfer level), and to perform a layout by automatic placement and routing based on the logic description. Since the function description is reflected on the LSI hardware, it is desirable that the function description be designed even earlier in consideration of the LSI hardware.

[0005] These two things are clearly contradictory. That is, the description is to try to describe / verify as far as possible from the LSI hardware, and to design in consideration of the LSI hardware. This will be described more specifically.

In the function design, it is desirable that "operation" and "condition" for performing the operation are paired. For example, as shown in Expression 1, the operation of the entire system is described by forming a pair of then indicating operation and if () indicating the condition, and the operation condition is changed by verification, or the operation condition is changed. Is added / deleted along with the condition. Therefore, the fact that the operation and its function are paired increases the efficiency of verification.

On the other hand, when considering the LSI in terms of the hardware structure, it can be roughly divided into an "arithmetic unit" and a "control unit", but the two are structurally different. The “arithmetic unit” is a part where regular operations are often repeated, and the “control unit” is a part where the control method varies depending on conditions. Therefore, the function description in which the "arithmetic unit" is separated facilitates hardware design. Also, if you project the "arithmetic unit" and "control unit" into the function description, you will see that "arithmetic unit" always corresponds to "operation", and "control unit" corresponds to "condition". . In the functional design, basically, it was not necessary to consider the number of “operations”. However, in actual hardware, the “number of operations” is related to the “number of arithmetic units” and has a very large meaning. Therefore, when considering the LSI hardware, it is desirable that the “operation” corresponding to the arithmetic unit is separated in the function description.

For example, the description shown in Expression 2 basically shows the same function as that shown in Expression 1, but since it is separated into a control part called CONT and an arithmetic unit called ALU, It is possible to optimally implement hardware of the control circuit having different characteristics. In particular, many arithmetic units have been studied for many years, and circuits and LSI layouts suitable for arithmetic operations have been made, so such descriptions can be directly applied.

The description shown in Equation 1 indicates that the operations ADD and SUB are performed, but does not indicate where the operations are performed at all. Common sense is ADD
It is conceivable that a computing unit that performs SUB and a computing unit that performs SUB exist separately. On the other hand, the description shown in Expression 2 specifies that two operations, ADD and SUB, are performed by the same arithmetic unit called ALU.

As described above, a function description such as Equation 1 that facilitates creation / verification of a function description is very different from a function description such as Equation 2 that facilitates hardware design.
The solution is often to create two different functional descriptions. That is, a function description for function design and a function description for hardware design.

[0011]

The function description for facilitating the creation / verification of such a function description and the function description for facilitating the design of the hardware naturally describe exactly the same function. This is a different description. Conventionally, a designer has newly created a function description for hardware design while checking the function description for function design, and has verified that the contents are the same. However, even if it is a function description for a new hardware design, it first extracts a part of the "operation" description part and moves it. Then, a plurality of consistent "operations" are integrated into one arithmetic unit. It is nothing but the work that has been done.

Of these, the first half of the work is simply a rewrite in principle, and there are many physical conversions. The time required for this is in principle wasted time. In the latter half of the work, re-verification is essentially required for integrating a plurality of objects, but the time required for re-verification of a careless mistake due to re-description is considered to be wasted time.

As described above, conventionally, considerable effort has been devoted to non-essential parts in order to newly describe functions for hardware design.

Accordingly, the present invention has been made in view of such conventional circumstances, and a purpose thereof is to automatically generate a function description for hardware design from a function description for function design. It is an object of the present invention to provide an LSI design support device capable of performing the above.

[0015]

In order to achieve the above object, the present invention provides an operation description extracting means for extracting at least an operation description from a function description in which an operation and a condition for performing the operation are described; Presenting means for presenting the description extracted by the means, computing element candidate designating means for designating some or all of the behavioral description presented by the presenting means as computing element candidates, and designation by the computing element candidate designating means. A module generation unit for newly generating an operation description module corresponding to the operation unit candidate from the operation description obtained, and a plurality of operations when the plurality of operation descriptions are designated as the same operation unit candidate by the operation unit candidate designation unit. An operation condition inconsistency determining means for determining whether or not the conditions are inconsistent and issuing a warning when the conditions are inconsistent.

[0016]

According to the above construction, the present invention first extracts a part in which the operation is described in the function description, thereby extracting a computing unit candidate. Then, this is displayed, and a part to be actually designed as an arithmetic unit on the LSI is designated by the designer from these arithmetic unit candidates. Further, the operation unit is generated as a new module, and a function description in which the operation unit and the control unit are separated is automatically generated. At the same time, a new signal required when the operation unit and the control unit are separated is generated.

Also, when the designer designates a plurality of operation unit candidates as the same operation unit, a new module corresponding to the same operation unit is generated and a signal is generated.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an LSI design support apparatus according to the present invention.

Referring to FIG. 1, an LSI design support apparatus according to the present invention includes a behavior description extraction unit 1 for extracting a behavior description, a display unit 2 for presenting the extracted behavior description to a designer by display, and a displayed behavior. An operator candidate specifying unit 3 in which a part of the description is specified as an operator candidate by the designer, and a display unit 2 warns when the operation conditions are inconsistent when a plurality of operation descriptions are specified as the same operator candidate. And a module generation unit 5 that generates a new operation description module corresponding to the operation unit candidate from the specified operation description.

FIG. 2 is a conceptual diagram of the processing according to the present invention.
Shown in

As a first embodiment, an example will be described in which a function description for hardware design shown in Expression 4 is generated from a function description shown in Expression 3 using the design apparatus of the present invention.

The operation description is extracted by the operation description extraction unit 1 from the function description shown in Expression 3 and displayed on the display unit 2 (Expression 5). From this display, the designer has specified only the “shift” description from the arithmetic unit candidate specification unit 3, and the module generation unit 5 performs a module conversion process for only that part. At this time, a module name is required for modularization. Further, it is necessary to generate a new control signal. However, since one operation description is allocated to one module, only one control signal is required.

Since the designer has specified a module name of SHIFTTER and a signal name of E as an arithmetic unit for these items, the module generation unit 5 generates an operation description module corresponding to the arithmetic unit of SHIFTER having the control signal E. Then, the description part which was originally a shift operation is changed to a description for operating a computing unit called SHIFTER. If no module name or signal line name is specified, automatic generation is also possible.

Thus, a function description (Equation 4) that is directly conscious of hardware called SHIFTER is generated.

Next, as a second embodiment, an example will be described in which the design apparatus of the present invention is used to generate a function description for hardware design shown in equation 7 from the function description shown in equation 6.

As in the first embodiment, an operation description is extracted from the function description shown in Equation 6 and displayed (Equation 8). From the display, the designer has specified that the two operations of “add” and “sub” are operated by the same arithmetic unit of “ALU”. At this time, when it is specified that one operation unit performs a plurality of operations, if the operation conditions clearly contradict each other, the operation condition inconsistency determination unit 4 determines it.
A warning is issued using the display unit 2 or the like.

The number of newly generated control signals is one because only one operation unit performs two operations. However, depending on the design, it may be advantageous to generate as many control signals as the number of functions. In the present embodiment, since the control signal is instructed to be one, a control signal E is newly generated.

Note that the instruction from the designer can be indirectly given by a file or the like, and in this case, the function of presenting to the designer can be temporarily stopped.

(Equation 1) if (A = 1) then Z = ADD (C, D) if (B = 0) then Z = SUB (C, D) (Equation 2) module CONT (C, D, A, B) if (A = 1) then Z = ALU (C, D, ADD) if (B = 0) then Z = ALU (C, D, SUB) end module module ALU (IN1, IN2, OP) if (OP) = ADD) then Z = ADD (IN1, IN2) if (OP = SUB) then Z = SUB (IN1, IN2) end module (Equation 3) module: BLOCKKA (A, B, C, D) input: A [32 ], B [32], C [1], D
[1] output: Z [32] function: if (C [0] = 1) then Z [0:31] = shift (A [0: 3
1], B [0:31]) endif: if (D [0] = 1) then Z [0:31] = add (A [0:31],
B [0:31]) endif endmodule (Equation 4) module: BLOCKKA (A, B, C, D) input: A [32], B [32], C [1], D
[1] output: Z [32] use: SHIFTER function: if (C [0] = 1) then Z [0:31] = SHIFTER (A [0:
31], B [0:31], 1) endif: if (D [0] = 1) then Z [0:31] = add (A [0:31],
B [0:31]) endif: endmodule: module: SHIFTTER (BA, BB, E) input: BA [32], BB [32], E [1] output: BZ [32] function: if (E [0 ] = 1) then BZ [0:31] = shift (BA [0:
31, BB [0:31]) endif: endmodule: (Equation 5) module: BLOCKKA (A, B, C, D) Z [0:31] = shift (A [0:31], B
[0:31]) Z [0:31] = add (A [0:31], B [0: 3]
1]) (Equation 6) module: BLOCKB (A, B, C, D) input: A [32], B [32], C [1], D
[1] output: Z [32] function: if (C [0] = 1) then Z [0:31] = add (A [0:31],
B [0:31]); endif: if (D [0] = 1) then Z [0:31] = sub (A [0:31],
Endif: endmodule (Equation 7) module: BLOCKB (A, B, C, D) input: A [32], B [32], C [1], D
[1] output: Z [32] use: ALU function: if (C [0] = 1) then Z [0:31] = ALU (A [0:31],
B [0:31], 1); endif: if (D [0] = 1) then Z [0:31] = ALU (A [0:31],
B [0:31], 0); endif: endmodule: module: ALU (BA, BB, E) input: BA [32], BB [32], E [1] output: BZ [32] function: if ( E [0] = 1) then BZ [0:31] = sub (BA [0: 3
1], BB [0:31]) endif: if (E [0] = 0) then BZ [0:31] = add (BA [0: 3
1], BB [0:31]) endif: endmodule: (Equation 8) module: BLOCKKB (A, B, C, D) Z [0:31] = sub (A [0:31], B [0: 3
1]); Z [0:31] = add (A [0:31], B [0: 3]
1]);

[0030]

As described above, according to the present invention, a function description for hardware design can be semi-automatically generated based on a function description describing conditions and their operations. For this reason, at the function design stage, the design can be advanced without much consideration of the hardware restrictions. In addition, since the occurrence of easy mistakes due to a change in description can be drastically reduced, design efficiency is greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an LSI design support apparatus according to the present invention.

FIG. 2 is a conceptual diagram for explaining processing according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 operation description extraction unit 1 2 display unit 3 operation unit candidate designation unit 4 operation condition inconsistency determination unit 5 module generation unit

Claims (2)

(57) [Claims] 1. An operation description extraction unit for extracting at least an operation description from a function description describing an operation and a condition for performing the operation, a presentation unit for presenting a description extracted by the operation description extraction unit, An operation unit candidate specifying unit that specifies a part or all of the operation description presented by the unit as an operation unit candidate; and an operation description module corresponding to the operation unit candidate from the operation description specified by the operation unit candidate specification unit. An LSI design support device, comprising: a module generation unit for newly generating a module. 2. When a plurality of operation descriptions are designated as the same computing unit candidate by the computing unit candidate designating means, it is determined whether or not the plurality of operating conditions are inconsistent. 2. The LSI design support apparatus according to claim 1, further comprising an operating condition inconsistency discriminating means.