JP3215210B2 - Hardware design support system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CAD (Computer Aided Design) system for supporting hardware design.
The present invention relates to a hardware design support system that supports design using a hardware description language.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable increase in the scale of hardware to be designed, such as an LSI, and with this, design is supported from a higher-level process such as functional design in order to improve design efficiency. CAD systems have been developed.

In such a CAD system, a hardware description language (hereinafter referred to as HDL) for hardware design similar to a software programming language is used as input data.

[0004] Such HDLs are specified in a single description format, such as TDL for describing the connection of the logic circuit and DDL for describing the function of the logic circuit without being aware of the specific circuit configuration. Those that target the design level have been developed.

However, these languages were developed independently,
Since it is intended for a single design level, there is a problem that it is not possible to mix and describe these descriptions to perform a model description of the hardware to be designed and perform a mix-level simulation.

On the other hand, with the increase in the scale of hardware to be designed, a design method in which the design object is divided into a plurality of modules and a plurality of designers design in parallel for each module has become common. Was. In such a design method, an appropriate description format and description level differ for each module, or a description method differs depending on a designer. Therefore, a single HDL can be used to describe a model description in a plurality of description levels and description methods. It has been desired to be able to verify the model by performing a mix-level simulation.

[0007] Against such a background, recently, as an HDL capable of performing mixed-level simulation by mixing expressions of different design levels in one language, Ve
rilog-HDL and VHDL have been developed. Of these, VHDL was standardized by the IEEE in 1987, and is expected to be used in almost all designs in the future (references, approaches to hardware design by VHDL language description R. Lipset et al., Naoshi Sugiyama et al. ,
McGraw-Hill Publishing Co., Ltd., Digital Design
n with Verilog HDL Elieze
r Sternheim et al., Automata Pu
(blishing Company).

In these HDLs, delay and asynchronous operations can be handled, and a language specification is designed based on the concept of event-driven simulation (here, event-driven simulation is a module at a certain time). Only when the output signal value changes, the arithmetic processing is performed on the module having the output signal as an input, and the simulation proceeds. This method is a general method for dealing with the above-described delay and asynchronous operation. Widely used).

That is, the description of the statement that is the basis of the HDL is an event-driven description in which substitution to a signal is executed when a certain signal changes or when a certain time elapses.

For example, the operation of transferring the value of the signal D to the register R at the rise of the clock signal clk is performed by Ve
rilog-HDL describes as shown in FIG.
L is described as shown in FIG.

A unit of description of these parallel operations is called a process, and a signal serving as a trigger for starting the process is called a sensitivity list. In the above example, cl
k is the sensitivity list.

FIG. 31 is a VHDL functional description of a selector circuit that determines the value of signal MBA by referring to the address portions of tables TB and TA determined from the values of signals Q and RDT.

In the above example of transfer to the register R, the sensitivity list is a single signal. However, if the function of a combinational circuit as shown in FIG. 31 is described, generally the right side of an assignment statement and the conditional expression of a conditional statement Since it is necessary to describe all the signals that appear, the number of signals in the sensitivity list increases.

In the description shown in FIG. 31, Q (5),
Q (6), RDT (0), RDT (1), RDT
(2), RDT (3), TA (2), TA (3), TA
(4), TA (5), TA (6), TA (7), TA
(8), TB (2), TB (3), TB (4), TB
(5), TB (6), TB (7), TB (8), total 2
Zero signals are signals of the sensitivity list.

Here, in FIG. 31, for example, a partial bit Q (5 to 6) of an 8-bit signal Q is included in the sensitivity list.
), And the operation differs. That is, in the case of FIG. 31, the signals Q (0), Q (1), Q (2), Q
Even if a change occurs in (3), Q (4) and Q (7), the operation described in the process is not executed, but in the case of FIG. 32, the processing described in the process is performed. Become.

In describing the sensitivity list in this way, it is necessary to pay sufficient attention to the referenced part of the array signal.

In addition, even if the signals TA and TB are not included in the sensitivity list in FIG.
See) Not a grammatical error.

The reasons are as follows: (a) Update the MBA value only when a change (hereinafter referred to as an event) occurs in the values of RDT (0 to 3) and Q (5 to 6), and keep saving the value otherwise. Figure 3 if you want to
The description of 3 is correct.

(B) In the case of referring to only the MBA value updated when an event occurs for RDT (0 to 3) and Q (5 to 6) in the description of the upper layer using the module of FIG. 31, the description of FIG. 33 is correct.

This is because.

However, if the timing at which an event occurs in TA and TB is different from that in Q and RDT, and the value of MBA must always hold the value calculated in this process, the signal to be referred to is changed. The description in FIG. 33 is incorrect because all must be included in the sensitivity list. This is because, for example, if the signal Q is not included in the sensitivity list, the signal MBA is set to the value indicated in this process from the occurrence of the event on the signal Q to the occurrence of the event on the signals RDT, TA, and TB. Is not guaranteed.

Such a sensitivity list has not been found in conventional TDL, DDL and the like.
At the time of the description, it is necessary to consider the meaning of the operation to be described as described above.

This imposes a heavy burden on the designer at the time of model creation as compared with the conventional HDL. In particular, for a designer who has been designing using a logic circuit diagram, such a simulation is peculiar to such a simulation. The concept was unfamiliar and there was a problem that it was difficult to shift to HDL-based design.

In the function description of a complicated circuit such as the selector of FIG. 31, there are many mistakes in which a signal to be inserted into the sensitivity list is forgotten, and further, a mistake in which a signal required for the sensitivity list is forgotten is omitted. There is also a problem that debugging is increased because it is not found at the time of compilation and only appears as an unexpected operation at the time of simulation.

[0025]

As described above, the VHD
When a hardware description language such as L, Verilog-HDL that enables a mixed-level simulation is used to describe the function of the hardware to be designed, the concept of a sensitivity list common to those languages has been conventionally used. There is a problem that it is difficult for a designer who has designed with a circuit diagram to be familiar. Also,
If the hardware is complicated, the number of signals to be inserted into the sensitivity list increases, so that there is a problem that mistakes in forgetting to write necessary signals increase. Furthermore, there is also a problem that errors in forgetting to write necessary signals in the sensitivity list are not grammatically incorrect, so they are not found at compile time, and only appear as unexpected operations during simulation, so that debugging effort increases. .

The present invention has been made in view of the above circumstances, and provides a hardware design support system capable of reducing the burden of input by a hardware description language of a designer and improving design efficiency. The purpose is to do.

[0027]

According to the present invention, there is provided a hardware design support system comprising: a first extracting means for extracting a parallel operation description portion of hardware from a hardware description program to be designed; Second extraction means for extracting a candidate signal for a start condition signal from the extracted parallel operation description part; signal display means for displaying a candidate signal for a start condition signal extracted by the second extraction means; A signal selecting means for selecting a signal designated from among the signals displayed on the signal display means as a starting condition signal; and a parallel operation description part of the hardware description program, the starting condition signal selected by the signal selecting means being selected. And an editing means for inserting the information into the file.

Further, the hardware design support system according to the present invention comprises a first extracting means for extracting a parallel operation description portion of hardware from a hardware description program to be designed, and a parallel extracting means extracted by the first extracting means. Second extraction of a signal that is a candidate for a start condition signal from the operation description part
Extracting means, third extracting means for extracting a described sensitivity signal from the parallel operation description part extracted by the first extracting means, and a signal extracted by the second extracting means and the third extracting means. Comparing means for comparing the sensitivity signals extracted by the means, display means for displaying a comparison result of the comparing means, and a designated desired sensitivity signal based on the comparison result displayed on the display means. The apparatus is characterized by comprising signal selecting means for selecting, and editing means for inserting the sensitivity signal selected by the signal selecting means into the hardware description program.

[0029]

As a result, according to the present invention, the parallel operation description portion of the hardware is extracted from the description of the hardware to be designed by the first extracting means, and then the parallel operation description portion is referred to by the signal assignment statement for each parallel operation description portion. That is, a signal referred to in the parallel operation description portion, such as a signal appearing on the right side or a signal appearing in the condition part of the conditional statement, is extracted by the second extracting means as a candidate for the activation condition signal. Then, the extracted signal is displayed on the signal display means, a signal to be inserted into the parallel operation description portion is selected by the signal selection means from the displayed signal, and the selected signal is displayed by the editing means on the parallel operation description. Insert in the description part. Thus, the designer can select a signal to be inserted into the parallel operation description portion from the displayed signals while considering the intended hardware operation, and insert the signal into the parallel operation description portion. . In this case, forgetting to write the signal and typo in the signal name can be reduced. At the time of signal selection, a composite type (array or structural type) can be selected by a partial name in addition to selecting by the entire signal name.

Further, according to the present invention, the sensitivity signal described in the parallel operation description part in the hardware description language is extracted by the third extracting means, and the sensitivity signal and the signal extracted by the second extracting means are extracted. Are compared by the comparing means, and the result of the comparison is displayed on the display means. As a result, it is possible to check whether or not the description of the activation condition signal has been forgotten to be written in the portion where the activation condition signal is already described in the parallel operation description portion, or to insert a signal. As a result, the check can be performed not only when the description is first written but also after the description is updated.

Further, a signal to be additionally inserted as a desired signal into the portion where the start condition signal of the parallel operation description portion is described is selected from the comparison result displayed by the display device, and the selected signal is edited by the editing device. Insert into the hardware description program. Thereby, it is checked whether the sensitivity signal has been forgotten to be written in the hardware description program in which the activation condition signal is already described, and the signal which needs to be additionally inserted is selected and added.
It is possible to reduce omission of writing of the sensitivity signal.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a schematic configuration of a hardware design support system according to a first embodiment. In the figure, reference numeral 1 denotes an input unit, which is used by a designer to input an operation specification of hardware to be designed as a hardware description program.
The input unit 1 has a selection instructing unit 11 for giving an instruction for selecting a sensitivity list.

A control unit 2 is connected to the input unit 1, and a storage unit 3 and a display unit 4 are connected to the control unit 2.
Here, the control unit 2 outputs a control command to the storage unit 3 and the display unit 4, and includes a process extraction unit 21, a reference signal extraction unit 22, a sensitivity list signal selection unit 23.
And an editing unit 24.

The process extracting unit 21 extracts a parallel operation description unit of hardware as a process from the hardware description program input from the input unit 1.

The reference signal extraction unit 22 is a process extraction unit 2
A signal which is referred to in a parallel operation description part as a candidate of a process start condition signal at the time of simulation among the processes extracted from 1 is extracted. Here, among signals written in the process, substitution is performed. All signals appearing on the right side of the sentence, in the conditional expression of the conditional sentence, are extracted.

Sensitivity list signal selector 23
Is to select a signal to be inserted as a sensitivity list from reference signals displayed on a reference signal display section 41 (described later) of the display section 4 in accordance with an instruction from the selection instruction section 11.

The editing unit 24 edits the original hardware description program using the signals listed as the sensitivity list by the sensitivity list signal selection unit 23, and generates a hardware description program in which the sensitivity list is inserted. Like that.

The storage unit 3 stores a hardware description program input from the input unit 1 and a hardware description program into which the sensitivity list generated by the editing unit 24 is inserted.

The display unit 4 displays the hardware description program input from the input unit 1 and displays the signal extracted from the reference signal extraction unit 22 on the reference signal display unit 41 as a reference signal. ing.

Next, the operation of the embodiment configured as described above will be described.

In this case, a case where a hardware description program as shown in FIG. 2 is input from the input unit 1 will be described as an example.

The hardware description program shown in FIG. 2 includes a table TB determined from the values of the signals Q and RDT,
This is a description of a selector that determines the value of the signal MBA with reference to the address portion of the TA.

In this program, the declaration of the external terminal of the module selector is written in the first to seventh lines, and the operation of the circuit that occurs inside the module selector is described in the eighth to last lines. Have been. Of the 13th to 41st lines,
Process s which is the center of module selector
The operation of "select" is described.

Thus, the hardware description program shown in FIG. 2 is input, and the sensitivity list is automatically generated, so that the hardware description realizing the simulation that meets the intention of the designer is created in FIG. This will be described with reference to the flowchart shown in FIG.

First, assuming that the designer inputs the hardware description program shown in FIG. 2 from the input unit 1, the process extracting unit 21 extracts a process (step 30).
1). In this case, the process extracted by the process extracting unit 21 is obtained as shown in FIG. 4 by the portion A in the description shown in FIG.

Here, if the process does not exist, the process ends. However, in the description shown in FIG. 2, since the process exists (step 302), the process proceeds to the next step 303.

In step 303, the reference signal extracting section 22
, All signals appearing in the conditional expression of the conditional statement on the right side of the assignment statement are extracted as reference signals from the signals described in the process extracted by the process extracting unit 21.
In this case, the extracted reference signal is obtained as shown in FIG.

FIG. 5 shows a processing flow in the reference signal extracting section 22. Where extract (s,
L) is a procedure for putting the reference signal included in the sentence s into the set L. When the sentence s is a compound sentence, this procedure is called recursively.

First, LIST representing a set of reference signals appearing in the process extracted in step 501 is initialized to an empty set.

Next, at step 502, it is determined whether or not the processing has been completed for all the statements in this process. If not, ex.
Execute tract (s, L).

Next, after initializing L to an empty set (step 503), in step 504, different processing is executed depending on the type of the sentence s.

If the sentence s is if, a conditional expression is first extracted (step 505). And extract the signal that appears in the conditional expression

(Equation 1) Is performed (step 506).

Here, if

(Equation 2) Then, L = L, and the elements of L do not overlap. Then i
extrac for all statements s' on the then side of the f statement
t (s', L ') is executed, and L' is included in L (step 507). If the if statement has the else side, el
The same applies to the se side (step 50).
8).

Next, when the sentence s is a case sentence, a conditional expression is extracted in step 509 in the same manner as in the case of if described above, and a signal appearing in the conditional expression is extracted in step 510 and put into L. In step 511, extract (s',
L ′) is performed, and L ′ is included in L.

Next, when the sentence s is a signal assignment sentence, a signal appearing on the right side is extracted and put into L (step 512).

If the sentence s is any other sentence,
do nothing.

Next, when the extract (s, L) is completed, the set L of reference signals included in s is included in the set LIST of reference signals appearing in the sentence in the process (step 513).

Then, when extract (s, L) is executed for all the statements s in the process (step 50)
2) The LIST contains a set of reference signals in the process, and the procedure ends.

Returning to FIG. 3, the signal extracted by the reference signal extracting section 22 is displayed on the reference signal display section 41 of the display section 4 (step 304). In this case, the display of the reference signal on the reference signal display section 41 is as shown in FIG.

In this state, the designer refers to the signal displayed on the reference signal display section 41 and designates a signal to be inserted as a sensitivity list by the selection instructing section 11 of the input section 1 (step 305). . As a result, the sensitivity list signal selector 23 selects the selection instructing unit 1
A signal to be inserted as a sensitivity list is selected from the reference signals of the reference signal display unit 41 according to the instruction of 1.

Here, for example, when the designer sets RDT (0), RDT
Suppose that you want to update the MBA value only when an event occurs in DT (1 to 2), RDT (3), Q (5), and Q (6), and keep saving it at other times.
As shown in FIG. 7, the signals Q (5), Q (6), RDT
(0), RDT (1 to 2), and RDT (3) are selected by checking each.

Finally, the editing unit 24 automatically creates a hardware description program after the sensitivity list is inserted (step 306). in this case,
FIG. 8 shows a hardware description program after the sensitivity list is inserted.

If the timing at which the values of TA and TB change differs from that of Q and RDT and the MBA must always hold the value calculated in this process, the reference signal shown in FIG. All should be selected. In this case, the hardware description program after insertion of the sensitivity list is as shown in FIG.

Therefore, in this way, the reference signals Q (5), Q (6), R
DT (0), RDT (1 to 2), RDT (3), TA
(2), TA (3), TA (4), TA (5), TA
(6), TA (7), TA (8), TB (2), TB
(3), TB (4), TB (5), TB (6), TB
(7) The designer selects only signals that match the design intention from TB (8) and inserts them as a sensitivity list, so that mistakes such as forgetting to write the sensitivity list can be reliably prevented. .

Further, as shown in FIG. 2, from the hardware description program in which the sensitivity list is not inserted, the candidate of the signal to be inserted into the sensitivity list is extracted and displayed, so that the designer meets the intention of the design. By selecting a signal and inserting it into the description as a sensitivity list, a description of the sensitivity list can be created automatically.

As a result, a program description error that cannot be found at the time of compiling and causes an unexpected operation at the time of simulation can be minimized, and the man-hour and time required for the simulation can be reduced.

(Second Embodiment) In the first embodiment, a sensitivity list is extracted and displayed from a hardware description program into which a sensitivity list is not inserted, and a sensitivity list is created and inserted. In the second embodiment, the omission of the sensitivity list is checked for a hardware description program in which the sensitivity list is already inserted as shown in FIG.

FIG. 10 shows a schematic configuration of the second embodiment. In this case, the control unit 2 includes a sensitivity signal extracting unit 25 for extracting a sensitivity signal in addition to the configuration described in FIG. A comparison unit 26 is provided for comparing the reference signal extracted by the signal extraction unit 22 with the sensitivity signal extracted by the sensitivity signal extraction unit 25, and the result of comparison by the comparison unit 26 is displayed on the display unit 4. I have to. Other parts are the same as those in FIG. 1, and the same parts are denoted by the same reference numerals.

Now, it is assumed that the designer has input the hardware description program shown in FIG.

Then, the process extracting section 21 extracts a process. Next, among the signals described in the process extracted by the process extraction unit 21 by the reference signal extraction unit 22, all signals appearing on the right side of the assignment statement and in the conditional expression of the conditional statement are extracted as reference signals. The sensitivity signal extraction unit 25 extracts a sensitivity signal from the process extracted by the process extraction unit 21. The sensitivity signal in this case is obtained as shown in FIG.

Then, the reference signal extracted by the reference signal extraction unit 22 and the sensitivity signal extracted by the sensitivity signal extraction unit 25 are compared by a comparison unit 26. As a result of the comparison, the sensitivity in the reference signal is obtained. A signal that is not a signal is displayed on the display unit 4. The comparison result in this case is obtained as shown in FIG.

In this way, it is possible to check whether or not the sensitivity list has been omitted from the hardware description program in which the sensitivity list has already been inserted.

Then, from the signals displayed on the display unit 4, a signal to be additionally inserted into the sensitivity list is input to the input unit 1.
, The sensitivity list signal selector 23 selects a signal to be inserted as a sensitivity list.

If, for example, Q (5) and RDT (3) are selected from the signals displayed in FIG. 13, these selected signals are added to the sensitivity signal, and a new sensitivity list is added. Is generated, and finally, the editing unit 24 automatically creates a hardware description program after inserting the sensitivity list.

Accordingly, this makes it possible to check for omissions in the sensitivity list for a hardware description program in which a sensitivity list has already been inserted.

According to this method, the sensitivity list can be updated.

(Third Embodiment) In the first and second embodiments, the signals appearing in the conditional expressions of if and case and the signals appearing on the right side of the signal assignment statement are used as reference signals from the input hardware description program. Are all extracted and displayed.

However, in general, the signal appearing in the conditional expressions of if and case is a signal representing the control of the circuit (hereinafter referred to as a control signal), and the signal appearing on the right side of the signal assignment statement is a signal representing the operation data. Often (hereinafter, this is called a data signal).

Therefore, in the third embodiment, a mode for extracting and displaying only a control signal without including a data signal at the time of signal extraction and display is provided, and the process is started only by a change in the control signal.

FIG. 14 shows a schematic configuration of the third embodiment. In this case, the input section 1 has an extraction signal mode designation section 12 in addition to the configuration described in FIG. Others
It is the same as FIG. 1, and the same parts are denoted by the same reference numerals.

The extracted signal mode designating section 12 prepares the following three modes as extracted signal modes.

(A) Clock signal extraction mode (clock mode) (b) Control signal extraction mode (control mode) (c) All reference signal extraction modes (all mode) Specifies which of the modes (a) to (c) should be used to extract the sensitivity list.

Then, the reference signal extracting section 22 extracts a signal according to the designated mode.

FIG. 15 shows an algorithm for extracting a reference signal. Now, assuming that the hardware description program shown in FIG. 16 is input, the processing flow described below is executed in accordance with the extraction signal mode designated by the extraction signal mode designation unit 12 (step 1501).

First, when the extraction signal mode is the clock mode, only the signal having the 'event attribute' is extracted (step 1502), and the reference signal display unit 4
1, the signal shown in FIG. 17 is displayed.

When the extracted signal mode is the control mode, only the signal appearing in the condition part of if and case is extracted (step 1503), and the signal shown in FIG. You.

When the extraction signal mode is the all mode, all the signals to be referred to are extracted (step 1504), and the reference signal display section 41 displays the signals shown in FIG.

When the designer gives an instruction to the displayed reference signal from the selection instruction section 11 of the input section 1, the sensitivity list signal selection section 23 selects a signal to be inserted as a sensitivity list. This allows
In the editing unit 24, a hardware description program in which the reference signal selected by the designer is inserted into the sensitivity list is automatically created.

It is also possible to compare a signal extracted by the system in accordance with the designated mode with a sensitivity signal already inserted by the designer and display the result of the comparison.

Accordingly, when the extraction signal mode is designated by the extraction signal mode designation section 12 in this manner, the reference signal extraction section 22 extracts the signal of the designated mode. If there are many signals to be referenced in the hardware to be designed, the signals can be classified and extracted for each mode, so that a signal that the designer clearly determines to be out of the list of the activation condition signals before the signal selection is selected. Can be eliminated in stages, making it easier to select the signal.

(Fourth Embodiment) In the third embodiment, after a mode of an extracted signal is specified, a signal is extracted in accordance with the specified mode, and this is displayed. Although the signal to be inserted into the activity list is selected, in the fourth embodiment, the designer does not specify the mode before the extraction, and when the system extracts the signal, the clock signal, the clock signal Other control signals, other than all the reference signals are extracted separately,
Thereafter, at the time of displaying the extracted signal, the mode is designated by the extracted signal mode designating section 12 described in the third embodiment, and a signal according to these designated modes is selected from the extracted signals and displayed on the reference signal display section 41. Like that.

In this case, the same effects as in the third embodiment can be expected.

(Fifth Embodiment) In the first to fourth embodiments,
The signals to be displayed as signal candidates to be inserted into the sensitivity list of a certain process were all signals already referred to in the description of the process.

However, a circuit described by a designer generally includes a plurality of modules, and a plurality of processes in those modules often operate by using a certain signal as a trigger. Also, signals that control multiple processes often do not appear in the descriptions of those processes.

Therefore, in the fifth embodiment, a signal that is likely to be included in the sensitivity list in most processes by the designer is registered in advance, and is always displayed as a sensitivity list candidate. ing.

FIG. 20 shows a schematic configuration of the fifth embodiment. In this case, a candidate signal storage unit 5 is connected to the control unit 2 and a default value of a signal inserted in a sensitivity list by a designer in advance is set. The candidate signal is stored, and the default candidate signal is stored in the reference signal display unit 4 together with the reference signal.
1 is displayed. Other parts are the same as those in FIG. 1, and the same parts are denoted by the same reference numerals.

For example, as shown in FIG. 21, a module m capable of referring to a global signal named Clock
In the case where processes p1, p2, and p3 are included in 1, m2, and m3, Clock is not referred to in the descriptions of the processes p1 to p3.

However, if the designer stores the Clock in the candidate signal storage unit 5 when describing the process in the hierarchy of this circuit, the reference signal display unit 41 displays a signal including the Clock signal as shown in FIG. A list is displayed.

If the designer selects all the displayed signals using this, a description 23 obtained by inserting a sensitivity list into the description shown in FIG. 21 is obtained.

In the above example, the case of a global signal has been described, but the same applies to the case of a port signal of each module.

As a result, it is possible to reduce insertion errors in the sensitivity list of signals which do not appear in the description of the process and which can trigger a plurality of processes in the design.

In addition to displaying the signal stored in the candidate signal storage unit 5 as a reference signal and allowing the designer to select the signal, there is also a method of always adding the signal to the sensitivity list. In addition, in order to store the signal in the candidate signal storage unit 5, in the above example, the designer specifies the signal, and at this time,
Although the signal is stored in the candidate signal storage unit 5 when the signal can be referred to by the module, the system may cause the candidate signal storage unit 5 to store all the signals that can be referred to in a certain module, The signals described in the sensitivity list of the process already described in a certain module may be sequentially stored in the candidate signal storage unit 5, or the signals referred to in the description of the specified range may be stored in the system. May be extracted, and the designer may specify each mode as described in the third embodiment, and store the signal corresponding to the mode in the candidate signal storage unit 5.

Therefore, in this way, the candidate signal storage unit 5 stores the candidate signal to be inserted into the list of the activation condition signals, and the reference signal display unit 41 displays the stored candidate signal, and also displays a certain process. , Signals other than those appearing in the process description can be displayed as candidate signals. In this way, when a clock signal does not appear in the description of each process such that a plurality of processes in a certain design module operate in synchronization with this process, this clock signal is stored in the candidate signal storage means. This signal can be displayed together with other reference signals when the reference signal is displayed. In this manner, even if the signal does not appear directly in the description in the process, the omission of the start condition signal list can be reduced.

(Sixth Embodiment) In the first to fifth embodiments,
Although a signal name enclosed in parentheses is inserted after the reserved word process as a sensitivity list, there is also a method using a wait statement as a description method of the sensitivity list.

Therefore, in the sixth embodiment, before inserting the sensitivity list, the designer is made to select a method for describing the sensitivity list, and the description according to the method is output.

FIG. 24 shows a schematic configuration of the sixth embodiment. In this case, the input unit 1 has a sensitivity list insertion mode designating unit 13 in addition to the configuration described in FIG. Other parts are the same as those in FIG. 1, and the same parts are denoted by the same reference numerals.

The sensitivity list insertion mode designating section 13 selects the following two modes.

(A) A mode in which parentheses are inserted after a process (process mode) (b) A mode in which inserts are performed after wait on (wait mode) In the first embodiment described above, FIG. Although the hardware description program of FIG. 8 is generated from the description of No. 2 in the sixth embodiment, if the above-mentioned mode (b) wait mode is specified by the sensitivity list insertion mode specifying unit 13, the editing unit 24 of FIG. Can be generated. Even when the sensitivity list is written in wait on, the sensitivity list already written in the description can be compared with the reference signal, and the result can be displayed to check the sensitivity list for omission.

(Seventh Embodiment) In the first to sixth embodiments, the range of the description for extracting the sensitivity list is not specified, but the range is specified and the process is extracted in the specified range. , A sensitivity list for the process can be automatically generated and inserted.

FIG. 26 shows a schematic configuration of the seventh embodiment. In this case, the control section 2 has a range designating section 27 in addition to the configuration shown in FIG. Others are the same as those in FIG. 24, and the same portions are denoted by the same reference numerals.

The range designating section 27 sets the range of the description for extracting the sensitivity list to a set of description line numbers (l1, l).
2) Specified by (11 <12). If the description of the range specified here includes a plurality of processes, the process from the process extracting unit 21 to the editing unit 24 is performed. If this range is specified in the internal description of the process, the process extraction processing by the process extraction unit 21 is not performed, and the processing after the reference signal extraction unit 22 is performed.

For example, it is assumed that the VHDL description of FIG. 27 is input and the line numbers 11 = 12 and 12 = 16 are specified by the range specifying unit 13 (range (1)). At this time, the system extracts the control signal Clock from this range and displays it. Then, when the designer selects the above-described sixth embodiment mode (b) wait mode as the sensitivity list in the sensitivity list insertion mode specifying unit 5, the system generates a description as shown in (1) of FIG. . Similarly, when the processing after signal extraction is performed on the ranges (2) and (3) in FIG. 27, w in FIGS. 28 (2) and (3) is obtained.
The ait statement is inserted immediately before the statement of the line number 11 specified by the range specifying unit 27.

In the case where the range is specified, the reference signal list can be compared with the sensitivity list in the description, and the result can be displayed.

Therefore, in this way, the range specifying unit 27 specifies the range in which the process extraction and the reference signal extraction are to be performed in the description of the hardware to be designed. As a result, even for a large hardware description, the process extraction and the reference signal extraction processing are performed only in the necessary range specified by the designer, and it is possible to respond to the request of the designer at high speed. In addition, it is possible to reduce errors in entry of a start condition signal list for a hardware description in which a portion where a process is started differs depending on a signal.

(Eighth Embodiment) When a sensitivity list does not exist in a process description and there is no other wait statement for explicitly specifying stop / start of a process, the process enters an infinite loop. Therefore, no signal is extracted by the reference signal extracting unit 22 shown in FIG.
It is also conceivable to add a function of outputting a warning message when an it statement is not included, and warn the designer that the description may fall into an infinite loop.

[0117]

As described above, according to the present invention, when designing hardware using a hardware description language,
A sensitivity list of hardware description can be automatically generated, and a check mechanism for the description of the sensitivity list can be enhanced.
Hardware design support that reduces the designer's burden of inputting descriptions can be realized.

Further, when describing the function of a complicated circuit, there are many mistakes in which a signal to be inserted into the sensitivity list is forgotten, and a mistake in which a signal required for the sensitivity list is forgotten is grammatically stated. Because it is not an error, it is not discovered at compile time and only appears as an unexpected operation at the time of simulation, so there is a problem that debugging effort increases. By providing a process of designating a signal to be displayed as a list candidate signal, forgetting to write the sensitivity list signal can be minimized. Furthermore, by comparing the description in which the sensitivity list is inserted with the reference signal, it can be used for checking the sensitivity list created by the designer himself or modifying the sensitivity list after changing the description. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a hardware description program applied to the first embodiment.

FIG. 3 is a flowchart for explaining the operation of the first embodiment.

FIG. 4 is a diagram illustrating a process extracted by a process extracting unit according to the first embodiment.

FIG. 5 is a flowchart for explaining the operation of the reference signal extraction unit of the first embodiment.

FIG. 6 is a diagram showing an example of a reference signal extracted from the process of the first embodiment.

FIG. 7 is a diagram illustrating an example of selecting a signal to be inserted into a sensitivity list according to the first embodiment;

FIG. 8 is a diagram showing a hardware description program after the sensitivity list is inserted according to the first embodiment.

FIG. 9 is a diagram showing another hardware description program after the sensitivity list of the first embodiment is inserted.

FIG. 10 is a diagram showing a schematic configuration of a second embodiment of the present invention.

FIG. 11 is a diagram showing a hardware description program applied to the second embodiment.

FIG. 12 is a diagram illustrating a sensitivity signal extracted by a sensitivity extraction unit according to the second embodiment.

FIG. 13 is a diagram showing a signal list obtained by removing a sensitivity signal from a reference signal according to the second embodiment.

FIG. 14 is a diagram showing a schematic configuration of a third embodiment of the present invention.

FIG. 15 is a flowchart for explaining the operation of the third embodiment.

FIG. 16 is a diagram showing a hardware description program applied to the third embodiment.

FIG. 17 is a diagram showing reference signals displayed in the clock mode of the third embodiment.

FIG. 18 is a diagram showing reference signals displayed in the control mode of the third embodiment.

FIG. 19 is a diagram showing reference signals displayed in the all mode of the third embodiment.

FIG. 20 is a diagram showing a schematic configuration of a fifth embodiment of the present invention.

FIG. 21 is a diagram showing a hardware description program applied to the fifth embodiment.

FIG. 22 is a diagram showing an example of a signal displayed for a process p1 of the fifth embodiment.

FIG. 23 is a diagram showing a hardware description program after a sensitivity list is inserted according to the fifth embodiment.

FIG. 24 is a diagram showing a schematic configuration of a sixth embodiment of the present invention.

FIG. 25 is a diagram illustrating a hardware description program after a sensitivity list according to the sixth embodiment is inserted.

FIG. 26 is a diagram showing a schematic configuration of a seventh embodiment of the present invention.

FIG. 27 is a diagram showing a hardware description program applied to the seventh embodiment.

FIG. 28 is a diagram illustrating a hardware description program after a sensitivity list according to the seventh embodiment is inserted.

FIG. 29 is a view showing an example of description of signal substitution by the conventional Verilog-HDL.

FIG. 30 is a diagram showing a description example of signal substitution by conventional VHDL.

FIG. 31 is a view showing an example of description of a selector in the conventional VHDL.

FIG. 32 is a view showing a description example of a selector in the conventional VHDL.

FIG. 33 is a view showing an example of description of a selector in the conventional VHDL.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input part, 11 ... Selection instruction | indication part, 12 ... Extraction signal mode designation part, 13 ... Sensitivity list insertion mode designation part, 2 ... Control part, 21 ... Process extraction part, 22 ... Reference signal extraction part, 23 ... Sensitivity Activity list signal selector,
24: editing unit, 25: sensitivity signal extraction unit, 2
6 ... Comparison unit, 3 ... Storage unit, 4 ... Display unit, 41 ... Reference signal display unit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (2)

(57) [Claims] 1. A a first extraction means to extract the parallel operation descriptive portion of the hardware from the design target hardware description program, <br/> activation condition from the parallel operation description portion extracted from the first extraction means a second extraction means for extracting a signal which is a signal of the candidate, and the candidate of the start condition signal extracted from the second extraction unit
And signal display means that displays the composed signals, designated from among the displayed signal to the signal display unit
And wherein the signal selecting means for selecting a signal as the activation condition signal, that the start condition No. signal selected from said signal selecting means equipped and editing means for inserting in parallel operation descriptive portion of the hardware description program Hardware design support system. Wherein the first extracting means to extract the parallel operation descriptive portion of the hardware from the design target hardware description program, <br/> activation condition from the parallel operation description portion extracted from the first extraction means A second extraction unit for extracting a signal that is a signal candidate, and a parallel operation description part extracted by the first extraction unit.
The extracts et al, the sensitivity signal which is described
And 3 extraction means, comparison means for comparing the sensitivity signal extracted by the signal extracted by the second extracting means and the third extraction means, and display means for displaying a comparison result of said comparing means, said Instructed based on the comparison result displayed on the display means
Hardware design support comprising: signal selection means for selecting a desired desired sensitivity signal; and editing means for inserting the sensitivity signal selected by the signal selection means into the hardware description program. system.