JP2946973B2 - Description data converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to its hardware description languages the underlying hardware is input from an input device description data hardware description data the hardware used in the logic simulator using a hardware description language about the description data converter for converting the description language.

[0002]

2. Description of the Related Art Conventionally, a logic simulator has been used to check whether a designed logic circuit operates properly. When the logic simulator is used, each logic element constituting the logic circuit and the state of connection of these logic elements are expressed using a hardware description language.

[0003]

As described above, conventionally,
A circuit designer has expressed in a hardware description language one-to-one correspondence between individual logic elements and signals constituting the circuit. Therefore, for example, in the case where one type of clock is used for many circuit elements such as registers, it is necessary to describe in a hardware description language such that this clock and each of those circuit elements are associated with each other.
As the circuit becomes more complicated, the time required for circuit representation becomes longer, and the probability of occurrence of a description error increases accordingly.

An object of the present invention is to provide a description data conversion device capable of converting hardware description data input from a hardware description data input device into a hardware description language for input to a logic simulator. It is in.

[0005]

According to the first aspect of the present invention, a logic description storage means for storing a plurality of elements constituting one circuit and their connection relation as a logic description, and a part or a part of these elements. a common logical operation description storage means for storing for each of the signal that might be used in common to all associates the elements of the supply destination of these signals,
By using the description stored in these storage means,
And development means for developing the A description language is provided to describe the data converter.

[0006]

[0007]

That is, according to the first aspect of the present invention, the logical description stored in the logical description storing means and the common logical operation description stored in the common logical operation description storing means are used, and the hardware description similar to the conventional one is performed by the expanding means. I try to expand to languages. At this time, the common logical operation description stored in the common logical operation description storage means includes, for each signal that may be used in common for a part or all of the elements constituting the circuit, for each of these signals. Since the elements of the supply destination are expressed in association with each other, the signals are decomposed so as to correspond to the elements one-to-one, and are developed into a hardware description language.

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of a circuit configuration of a description data input conversion device used in an embodiment of the present invention. The description data converter 10 includes a CPU (Central Processing Unit) 11. The CPU 11 is connected to a working memory 13, an input circuit 14, a magnetic disk control device 15, a display control circuit 16, and a printer control device 17 via a bus 12 such as a data bus.

The work memory 13 is a random access memory for storing a program for controlling the description data input conversion device 10 and data temporarily required for the control. The input circuit 14 is connected to a keyboard 22 to which a mouse 21 as a pointing device is connected, and inputs data from these devices. Magnetic disk controller 15
Is connected to the magnetic disk 23. Magnetic disk 2
Reference numeral 3 stores a program to be transferred to the work memory 13 and also stores a hardware description language created by this apparatus and other data. The display control device 16 is connected to the CRT 24 and performs this display control. The printer control device 17 is connected to the printer 25 and prints out a hardware description language or the like as needed.

[0013] Figure 2 is intended to illustrate the relationship between the description data input conversion device and the logical simulator.
The description data input conversion device 10 of this embodiment inputs a hardware description for inputting a description of a designed predetermined circuit (step S101), and generates a hardware description language based on the input. (Step S10
Through the two steps of 2), the data input from the keyboard 22 or the like is converted into a hardware description language. The hardware description language created in this way is input to the logic simulator 31, and the designed circuit is verified.

FIG. 3 shows the basic configuration of the description data input conversion device of this embodiment. The description data input conversion device 10 is used in common with a part or all of these elements, and a logical description input unit 32 for inputting a plurality of elements constituting one circuit and their connection relations as a logical description. It has two input means, a common logic operation description input means 33 for inputting the elements to which these signals are supplied in association with each of the possible signals. This corresponds to the hardware description data input device according to the first aspect of the present invention.

The logical description input from the logical description input means 32 is stored in the logical description storage means 34. The common logical operation description input from the common logical operation description input unit 33 is stored in the common logical operation description storage unit 35. The description data stored in these storage units 34 and 35 is input to the expansion unit 36 and expanded, and the hardware description language is output. This corresponds to the description data conversion device according to the second aspect of the present invention.

FIG. 4 shows an example of a circuit represented by the logical description input from the logical description input means. The circuit 41 includes four registers 42 to 45 of A, B, C, and D, and one AND gate 46. The AND gate 46 has two registers 42, 4
5, and the contents are stored in a register 43. The register 44 is arranged next to the register 43.

The circuit 41 shown in FIG. 4 is input in a hardware description language by a description method similar to the conventional one. The input hardware description language is stored in a logical description storage area (logical description storage means 34) in the working memory 13.

FIG. 5 shows an example of the common logical operation description input from the common logical operation description input means. Here, the first description 51 is a description example of a reset definition statement. This description 51 corresponds to the dependent “A” register 42
And the "B" register 43 defines the asynchronous reset signal "RST" to be "0". The following description 52 shows a clock definition statement. In this example, a clock signal is defined in all the registers 42 to 45. In addition, these registers 42 to 45 are set as “clock-edge-up” at the rise of the clock signal.
Is triggered. Further description 53
Indicates a hold definition statement. Here, the hold signal HLD is defined in the subordinate "A" register 42.

The signals such as the reset signal and the clock signal which may be supplied in common to a plurality of circuit elements are common logic operation description input means described in FIG. From 33, a description sentence in the form as shown in FIG. 5 is input and stored in the common logic operation description storage means 35.

FIG. 6 shows a common logical operation description input from the common logical operation description input means. Here, the clock signal CLK ₁ in the first description 54 "A", "B" and "C" of the three registers 42,4
3, 44 and are shown to be triggered on these rises. Further, the following description 55 indicates that another clock signal CLK ₂ is supplied to the “D” register 45 and is triggered by this rising. The input common logical operation description is stored in the common logical operation description storage area (common logical operation description storage means 35) in the working memory 13.

The input terminal connected to the register 42 of the circuit 41 shown in FIG. 4 is denoted by IA, the input terminal connected to the other register 45 is denoted by IB, and
The output terminal connected to 4 is an IC. In this case, description data combining the logical description and the common logical operation description input to the description data input conversion device is as follows, for example.

[0022]

INPUT IA, IB; OUTPUT IC; register: A, B, C, D; clock-edge-up CLK1 ｛A, B,
C｝; clock-edge-up CLK2 ｛D｝; A = IA; D = IB; B = A * D; C = B; IC = C;

Here, the AND gate 46 of the circuit 41 shown in FIG. 4 is represented by the description "B = A * D;". The description in the latter half including this description is the logical description of the circuit 41 shown in FIG.

FIG. 7 is shown in FIGS. 5 and 6 of two or more
FIG. 2 shows a state of a circuit described by a hardware description language created based on one description. Basic connection state of the circuit shown in FIG. 4, the clock signal C
A supply path for LK ₁ and another clock signal CLK ₂ is added,
It is shown that the final circuit has been configured.

FIG. 8 shows an outline of the control operation of the description data input conversion device of this embodiment. First, the CPU 11 shown in FIG. 1 reads description data necessary for describing a circuit in a hardware description language (step S201). These correspond to the logic description input means 32 and the common logic operation description input means 33 as described in FIG.
The result is stored in the hardware description storage means 61 (work memory 13 shown in FIG. 1).

Next, the CPU 11 reads the description data stored in the hardware description storage means 61 and performs a syntax analysis process (step S202). Then, the editing process of the hardware description language is performed (step S203), and the hardware description language 62 is output.

FIG. 9 shows a state of the syntax analysis processing in step S202. In the syntax analysis process, first, the common logical operation description analysis process input by the common logical operation description input unit 33 is performed (step S301). Next, the logical description analysis processing input from the logical description input means 32 is performed (step S3).
02).

FIG. 10 shows a schematic operation flow of the common logic operation description analysis processing. Here, it is assumed that the definition statement to be the target of the common logic operation description is composed of three types, a reset definition statement, a clock definition statement, and a hold definition statement as shown in FIG. In this case, analysis processing is first performed on the reset definition statement (step S401), then analysis processing is performed on the clock definition statement (step S402), and finally analysis processing is performed on the hold definition statement (step S403). ). In addition to this, when defining a definition sentence to be described in the common logical operation description, more analysis processing is performed.

FIG. 11 shows a more specific flow of the common logic operation description analysis processing in this embodiment. The CPU 11 shown in FIG.
It is determined whether or not the first phrase of the description data read from is a common logical operation description (step S50)
1). If it is not the common logical operation description (N), it is not necessary to perform the common logical operation description analysis processing, so the processing is terminated (END).

If the description is a common logical operation description (Y), it is determined whether or not the leading phrase is a register declaration (step S502). Here, the register declaration is a declaration indicating a signal supplied to the register, such as “register” in the above described description data. In this case (Y), the register signal name is stored in a predetermined location of the working memory 13 (step S503). If it is not a register declaration (N), the process immediately proceeds to step S504.

In step S504, it is determined whether the head phrase is a memory declaration. Here, the memory declaration is a declaration indicating a signal supplied to the memory, such as “memory”. In this case (Y), the memory signal name is stored in a predetermined location of the working memory 13 (step S505). If it is not a memory declaration (N), the process immediately proceeds to step S506.

In step S506, it is determined whether the head phrase is a reset definition sentence, a clock definition sentence, or a hold definition sentence. If it is a reset definition statement, the reset definition statement is analyzed (step S507), and the reset type, reset signal name, and target register name are stored in predetermined areas of the working memory 13 (step S508). ).

On the other hand, if it is a clock definition statement, the clock definition statement is analyzed (step S50).
9) The clock type, clock signal name, and target register name are stored in predetermined areas of the working memory 13 (step S510). Step S50
If it is determined in step 6 that the statement is a hold definition statement, the hold definition statement is analyzed (step S511), and the hold signal name and the target register name are stored in predetermined areas of the working memory 13, respectively. (Step S51
2). Thus, the common logic operation description analysis processing ends (end).

FIG. 12 specifically shows the state of the logic description analysis processing in step S302 of FIG. First, the CPU 11 reads the description data of the logical description read from the magnetic disk 23, stores the left side and the right side in separate areas (step S601), and compares the left side signal name with the register signal name (step S602). ).
If they match (Y), processing as a register statement is performed (step S604), and the comparison with the reset, clock, and hold signal names is determined (step S605). Then, the process proceeds to step S606. If they do not match in step S603, the above steps are omitted and the process proceeds to step S606.

In step S606, the stored signal name on the left side is compared with the memory signal name. If they match (step S607; Y), processing as a memory statement is performed (step S608). If they do not match (step S607; N), processing as a terminal statement is performed (step S609).

FIG. 13 shows details of the hardware description language editing processing shown in step S203 after the syntax analysis processing shown in step S202 in FIG. 8 is completed as described above. The CPU 11 checks whether the left side of the logical description is a register statement (step S701). If the sentence is a register sentence, a register sentence is output at the beginning of the sentence (step S702), and then the left side is output (step S703). Next, it is determined whether the sentence is a reset sentence (step S704). If so (Y), a reset modifier sentence is output (step S7).
05).

Subsequently, the CPU 11 determines whether or not it is a clock statement (step S706), and if so, outputs a clock modification statement (step S707), and determines whether or not it is a hold statement (step S708). . If the sentence is a hold sentence (Y), a hold modifier sentence is output (step S709). Then, the right side is output (step S710), and the editing process ends (END). If it is determined in step S706 that the sentence is not a clock statement (N), the right side is output immediately (step S710), and the process ends (END).
The same applies to the case where it is determined in step S708 that the sentence is not a hold statement (N).

On the other hand, if it is determined in step S701 that the statement is not a register statement but a memory statement or a terminal statement, each statement is output at the beginning of the statement (step S711).
The left side and the right side stored in step S601 are output as they are (step S712), and the process ends (END). Thus, an example of a hardware description language finally created for the circuit shown in FIG. 7 is as follows.

[0039]

INPUT IA, IB; OUTPUT IC; REG A = IF CLK1. UP. THEN IA; REG D = IF CLK2. UP. THEN IB; REG D = IF CLK1. UP. THEN A * D; REG C = IF CLK1. UP. THEN B; TER IC = C;

[0040]

According to the first aspect of the present invention, as described above, a hardware description is made based on a logical description and a common logical operation description.
A hardware description language is generated, so quality
There is an effect that unified description becomes possible.

[0041]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a circuit configuration of a description data input conversion device used in an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a description data input conversion device and a logic simulator.

FIG. 3 is an explanatory diagram showing a basic configuration of a description data input conversion device.

FIG. 4 is a circuit diagram illustrating an example of a circuit represented by a logical description input from a logical description input unit.

FIG. 5 is an explanatory diagram showing an example of a common logical operation description input from a common logical operation description input unit.

FIG. 6 is an explanatory diagram showing a common logical operation description input from a common logical operation description input unit.

FIG. 7 is a circuit diagram described by a hardware description language created based on the two descriptions shown in FIGS. 5 and 6 .

FIG. 8 is a flowchart showing an outline of a control operation of the description data input conversion device of the present embodiment.

FIG. 9 is a flowchart showing the syntax analysis processing in step S202.

FIG. 10 is a flowchart showing a schematic operation flow of a common logic operation description analysis process.

FIG. 11 is a flowchart showing a specific flow of a common logic operation description analysis process in the embodiment.

FIG. 12 is a flowchart specifically showing a state of a logical description analysis process in step S302 of FIG. 9;

FIG. 13 is a flowchart showing details of a hardware description language editing process shown in step S203.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Description data converter 11 CPU 13 Working memory 14 Input circuit 22 Keyboard 23 Magnetic disk 32 Logical description input means 33 Common logical operation description input means 34 Logical description storage means 35 Common logical operation description storage means 36 Expansion means 41 Circuit 61 Hardware Hardware description storage means 62 Hardware description language

Claims (1)

(57) [Claims] A logic description storage means for storing a plurality of elements constituting one circuit and their connection relations as a logic description, and a logic description storage means commonly used for a part or all of these elements. Common logic operation description storage means for storing , in association with each possible signal, elements to which these signals are supplied
And the hardware using the descriptions stored in these storage means.
Description data converting apparatus characterized by comprising a deployment means for deploying the A description language.