JPS62224947A - Compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a second layer wiring having no leak by a method wherein the side surfaces of a gate electrode are formed in such a way as to make an angle of nearly 90 deg. with the surface of a substrate and the side surfaces of a first layer wiring are formed in such a way as to make an acute angle with the substrate surface. CONSTITUTION:A first layer wiring 14 is formed of a tungsten layer of 4,000Angstrom , the same thickness as that of a gate electrode 13. The side surfaces 15 of the first layer are wiring are formed in such a way as to form an acute angle with a semi-insulative gallium-arsenic substrate 11. Metal 41 for a second layer wiring is left behind an interlayer insulating film 29 in a gate electrode part 23, but the parts of shadows are not formed on the interlayer insulating film in the first layer wiring part. Therefore, no leak is generated between a second layer wiring 25 and another second layer wiring 26. There is a possibility that the metal for a second layer wiring is left on parts 28 in the gate electrode part, but the metal for a second layer wiring is not left on parts 29. Therefore, no leak is generated between a second layer wiring 27 and the second wiring layer 26. Moreover, by forming the side surfaces 16 of the gate electrode in such a way as to become vertical to the substrate surface, the efficiency of the field-effect transistor can be accurately controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION Integrated circuits using field effect transistors as basic elements using compound semiconductors as active layers are capable of faster operation than silicon integrated circuits, and are currently being developed.

In a field effect transistor whose operating layer is gallium arsenide, which is one of compound semiconductors, the gate electrode is formed of a metal layer, so the metal layer is also used for the first layer wiring. The length of the gate electrode is an important factor that determines the performance of a field effect transistor, and in order to improve its dimensional accuracy, a dry etching method is used to form the gate electrode, and the sides of the gate electrode metal layer are aligned with the substrate surface. It is formed to form an angle of approximately 90°. Since this metal layer is also used as the 11th layer wiring, the side surfaces of the 1st layer wiring are also formed at an angle of approximately 90° with the substrate surface.

(Problems to be Solved) In order to form an integrated circuit, it is necessary to further deposit an interlayer insulating film and form a second layer wiring on top of it. However, if the side surface of the first layer wiring 32 forms an angle of 90 degrees with the surface of the substrate 31 as shown in the one-fold structural diagram of FIG. 34 remains, which may cause leakage between the second layer wirings.

An object of the present invention is to provide a compound semiconductor integrated circuit that solves this problem.

(Means for Solving the Problems) The present invention provides a compound semiconductor integrated circuit in which the gate electrode of a field effect transistor and the first layer wiring are formed of the same material, in which the side surface of the gate electrode is at approximately 90 degrees with the substrate surface. The compound semiconductor integrated circuit is characterized in that the side surface of the first layer wiring forms an acute angle with the substrate surface.

(Function) In the present invention, it is important that the side surfaces of the gate electrode section and the first layer wiring section formed of the same material have different angles with the substrate surface. Since it forms an acute angle with the substrate surface, no metal for the second layer wiring remains behind the interlayer insulating film, and a leak-free second layer wiring can be formed.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. Figure 1 (
a) is a plan view for explaining one embodiment of the present invention. In FIG. 1(a), 11 is a semi-insulating gallium arsenide substrate, 12 is an n-type gallium arsenide operating layer, and 13 is a gate electrode, which is formed of, for example, a tungsten layer with a thickness of 4000 μm, and when a voltage is applied, n-type GaAs operating layer 12
change the effective thickness of the Further, 14 is a first layer wiring, which is formed of a tungsten layer having the same thickness as the gate electrode and having a thickness of 4000 nm. FIG. 1(b) is a cross-sectional view taken along the dashed line in FIG. 1(a), that is, a cross-sectional view of the first layer wiring, in which the side surface 15 of the wiring forms an acute angle with respect to the surface of the semi-insulating gallium arsenide substrate. It shows what you are doing. Figure 1 (
C) is a 1-fold view taken along the dashed line C in FIG.
This shows that it forms an angle of . FIG. 2(a) is a plan view showing a state in which a second layer wiring is formed by a dry etching method after depositing an interlayer insulating film from the state shown in FIG. 1(a), and 23 is a gate electrode, 24 is the first layer wiring, 2
5, 26, and 27 are second layer wirings. A cross-sectional view along the dashed-dotted line in this state is shown in FIG. 2(b), and a cross-sectional view along the dashed-dotted line C is shown in FIG. 2(e). Figure 2 (
As shown in e), the second layer wiring metal 41 remains behind the interlayer insulating film 29 in the gate electrode part, but in the first layer wiring part, the interlayer insulating film 29 remains as shown in FIG. 2(b). Since there is no shaded area, the second layer wiring 25 and other second layer wiring 2
No leakage occurs between 6 and 6. Furthermore, in the gate electrode part, there is a possibility that the metal for the second layer wiring remains in the part indicated by 28 in FIG. 2(a), but the metal for the second layer wiring remains in the part indicated by 29. Since no trace remains, no leakage occurs between the second layer wiring 27 and other second layer wirings 26. Further, by making the side surface 16 of the gate electrode perpendicular to the substrate surface, the performance of the field effect transistor can be controlled with high precision. In this case, if the sides of the gate I electrode are not formed perpendicular to the substrate surface, it will not function well as a mask, and silicon ions will be implanted even under the gate electrode. Put it away.

In addition, in order to obtain the structure as shown in FIG. 1(C), for example,
Tungsten can be processed by reactive ion etching using a mixed gas of SF6 and CF4 using photoresist as a mask.For example, to obtain the structure shown in Figure 1(b), use SF6 gas using photoresist as a mask. Tungsten can be processed using reactive ion etching.

In the above embodiments, tungsten was used as the material for the gate electrode and the first layer wiring, but other metals, metal compounds, or silicides thereof may also be used. Furthermore, although a semi-insulating gallium arsenide substrate is used as the substrate, other compound semiconductor substrates may be used.

(Effects of the Invention) As described above, in the compound semiconductor integrated circuit obtained by the present invention, the side surfaces of the gate electrode are vertical.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining one embodiment of the present invention, in which (a) is a plan view, and (b) is a 1-point view along the dashed line.
The folded view (C) is a sectional view taken along the dashed line C. In the figure, 11.21 is a semi-insulating gallium arsenide substrate,
12 is the n-type gallium arsenide active layer, 13.23 is the gate electrode, 14.24 is the first layer wiring, 15 is the side surface of the first layer wiring, 16 is the side surface of the gate electrode, 25, 26.27 is the second layer Wiring, 28 is the remaining part of the second layer wiring metal, 29
4 is a portion where no second-layer wiring metal remains, and 41 is a second-layer wiring metal. FIG. 3 is a cross-sectional view for explaining problems in the conventional first layer wiring, in which 31 is a substrate, 32 is a first layer wiring, 33 is an interlayer insulating film, and 34 is a metal for second layer wiring. Engineering::1゛Country;,,,,(,:1 President u, -1!-Child p Takashi ζ Tanuki potassium 2 ratio system 11 and a half 2
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Claims (1)

[Claims] In a compound semiconductor integrated circuit in which the gate electrode of a field effect transistor and the first layer wiring are formed of the same material, the side surface of the gate electrode forms an approximately 90° angle with the substrate surface, and the side surface of the first layer wiring forms an angle of approximately 90° with the substrate surface. A compound semiconductor integrated circuit characterized by an acute angle.