JPS5994439A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simultaneously enable to prevent the disconnection of wirings and to accurately control the channel length by simultaneously forming a gate electrode having a vertical side face and the wiring of tapered side face on the same film surface in a substrate. CONSTITUTION:An Mo layer 10 having low oxygen density and an Mo layer 11 having high oxygen density are superposed on a field oxidized film 2 and a gate oxidized film 6 of a P type Si substrate 1, the layer 11 is selectively removed, and a resist mask 13 is covered. An Mo gate electrode 14, tapered Mo wirings 15 and Mo film 16 are formed by parallel flat plate type plasma etching on the vertial side face. An N type source 8 and drain 9 are formed, an interlayer insulating film 17 is accumulated and opened, and aluminum wirings 18 are attached. When the oxygen density of the Mo layer is increased from 3 atomic % to 20 atomic %, the tapered angle can be reduced from 90 deg. to 40 deg., the Mo wiring film can be increased in thickness without disconnecting the aluminum wirings nor increasing the resistance on the Mo wirings, accelerated by reducing the resistance, and the channel length can be accurately controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device suitable for use in a semiconductor integrated circuit and a method for manufacturing the same, and particularly relates to a semiconductor device having an etched side profile perpendicular to a substrate surface. The present invention relates to a semiconductor device in which a gate electrode portion and a tapered wiring portion are continuous and in the same metal film plane, and a method for manufacturing the same.

[Prior art]

Conventionally, electrodes and wiring for high-density semiconductor integrated circuits have been formed using a dry etching method so that the etched side surface is perpendicular to the substrate surface and has a tapered shape. The dry etching method involves etching electrodes and wiring materials in a gas plasma formed by an inert gas or a reactive gas. One type has a side surface that is perpendicular to the substrate surface (hereinafter, this shape will be referred to as vertical, and this method will be referred to as the vertical etching method), and the other type has a side surface that is inclined in a tenon shape with respect to the substrate surface. There are two types of taper etch methods.

Hereinafter, the conventional processing shape of electrode wiring and its processing technology will be described, taking as an example the case where word lines of an MO8 type integrated circuit are formed using MO (molybdenum), a high-melting point metal, as the electrode/wiring material. Note that the word line referred to here refers to the gate electrode of the switching MOS transistor in the MO8 type integrated circuit and the wiring from the power source for applying voltage to the gate electrode, and is formed of the same layer of the same material. There is. Therefore, the word line is composed of two consecutive parts: the gate electrode part and the wiring part.

As a first conventional example, when a vertical etching method is used to form word lines, M
We will take up the process of manufacturing the wiring part of the o word line, and explain a part of it using drawings. Figure 1(a)-(d)
FIG. 2 is an explanatory diagram of the manufacturing process of the wiring of the conventional semiconductor device. Without trenches, a Si oxide film 2 for element isolation is formed on the surface of the Si substrate 10, as shown in FIG. 1(a). Next, as shown in FIG. 1(b), after gate oxidation (the gate oxide film is not shown), a Mo thin film 6 for wiring is deposited by the S/Q ivy method or the electron beam evaporation method. On top of that, Figure 1 (C)
As shown in FIG. 2, the resist ζ turf 4 is formed by applying a resist and then performing exposure, development, etc. using a patterned mask. Next, Figure 1 (d
), the Mo thin film 6 is etched in a mixed gas plasma of CCl4 and 02 using, for example, an anode-coupled parallel plate electrode type plasma etching method.
o Form the word line wiring section 5. Thereafter, the resist pattern 4 is removed using a plasma associator, thereby completing the MO word line wiring pattern.

Although the subsequent steps are not shown, the MOS
Processes such as ion implantation and annealing to form a transistor, formation of an interlayer insulating film, and formation of a second layer wiring are then carried out to complete the wiring portion of the word line.

Due to the characteristics of the parallel plate electrode type plasma etching method, the side shape of the MO word line wiring section 5 formed in this way is perpendicular to the surface of the underlying Si oxide film 2, and the side shape is vertical to the surface of the underlying Si oxide film 2. Because there is little etching, resist
Dimensional changes with respect to the pattern are small and exhibits high processing accuracy. However, when an interlayer insulating film is formed on this Mo word line and a second layer wiring made of A7 or the like is formed on top of that, the steep step shape on the side surface of the Mo word line is caused by the interlayer insulating film. It is also reflected on the surface. Therefore, the second layer wiring cannot maintain a sufficient film thickness at this stepped portion, and there is a disadvantage in that the resistance is likely to increase due to a decrease in film thickness, even if it does not lead to disconnection. In fact, since a reverse tapered overhang portion is formed on the side surface of the interlayer insulating film, etching remains of Al are likely to occur in this portion, which causes a short circuit in the seventh layer wiring.

On the other hand, the gate electrode portion of the Mo word line having vertical side surfaces formed at the same time as the Mo word line wiring portion 5 has a so-called self-alignment structure that automatically aligns the source and drain regions and the gate electrode. Used as a gate. That is, the gate electrode part is used as a mask for ion implantation to form the source and drain regions, and due to its vertical side shape and high processing accuracy, the channel length between the source and drain regions (below the gate electrode) is (distance from the edge of the source region near the surface of the Si substrate to the edge of the drain region)
can be determined with good reproducibility and high precision.

Variations in channel length are the cause of variations in threshold voltage (voltage applied to the gate electrode necessary to form a channel near the surface of the Si substrate below the gate electrode), which is an important characteristic of MO8) transistors. Become. Therefore, the vertical etching method, which can control pattern changes from resist dimensions to a small extent, is suitable for processing the gate electrode portion.

As a second conventional example, in the case where a taper etching method is used to form word lines, a process of manufacturing a gate electrode portion of an MO word line will be taken up, and a part thereof will be explained with reference to the drawings. FIGS. 2(a) to 2(e) are explanatory views of the manufacturing process of the gate electrode.

Instead, as shown in FIG. 2 (I), an S+ oxide film 2 for isolation between elements is formed on the surface of the Sl substrate 1. Next, as shown in FIG. 2(1)), after forming the gate oxide film 6,
A Mo thin film 6 is produced using either the spuck method 1 or the electron beam evaporation method.
deposit. Thereafter, as shown in FIG. 2(C), the resist with tapered side surfaces was formed by controlling the exposure conditions.
A pattern 41 is formed. Next, as shown in FIG. 2(d), by the ion etching method,! 111M0 thin film 6
A tapered MO gate electrode 7 is formed by etching. At this time, the resist pattern 41 whose side surfaces are tapered is also etched, resulting in a thin resist pattern 42 while maintaining the approximate inclination angle. However, if there is no taper on the side surface of the resist pattern before etching, the resist pattern will not be narrowed in this way. This etching method takes advantage of the fact that the resist pattern itself is etched and narrowed as the Mo thin film is etched to obtain a tapered shape of the gate electrode. Next, as shown in FIG. 2(e),
Impurity ions having a conductivity type opposite to that of the Si substrate 1 are implanted using the -type MO gate electrode 7 as a mask, and 1Vi
A source region 8 and a drain region 9 of the OS transistor are formed. Thereafter, annealing is performed at a temperature of 1 (t00° C.) to activate impurities.

However, the Mo word line gate electrode portion formed in this manner has a drawback that, due to the characteristics of the taper etching method, the gate electrode width W2 after etching is narrower than the resist pattern width W1 before etching. . It is difficult to accurately control the amount of decrease from Wl to W2. Furthermore, the bottom portion of the tapered MO gate electrode 7 in contact with the source and drain regions 8.9 does not have sufficient masking properties against ion implantation, and impurity ions pass through and reach the Si substrate 1 in a trench. As a result, it becomes difficult to accurately control the channel length between the source region 8 and the drain region 9, resulting in a disadvantage that transistor performance deteriorates.

On the other hand, in the word line formed by the taper etching method, since the side surfaces are tapered, problems such as disconnection of the second layer wiring that occur when the vertical etching method is used are less likely to occur.

As explained above, it is desirable that the side shape of the word line of the MO8 type integrated circuit is perpendicular to the underlying substrate surface in the gate electrode portion, and tapered in the wiring portion. However, in the conventional +vros type integrated circuit, there is no word line that has a vertical gate electrode part and a tapered wiring part at the same time. It is not possible to form both side shapes at the same time.

[Purpose of the invention]

It is an object of the present invention to solve the above-mentioned problems in the prior art, and to provide a semiconductor device having tapered and vertical image shapes as side shapes of electrodes and wirings in the same metal film plane, and An object of the present invention is to provide a manufacturing method for simultaneously forming.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized by a step of forming an upper and lower two-layer structure metal film on a semiconductor substrate, in which the upper layer has a higher oxygen concentration than the lower layer, and one of the two-layer structure metal films. a step of performing first patterning only on the upper layer of the part;
Next, by performing second patterning on the entire surface, the lower etched side surface of the metal film with the upper layer is tapered to the substrate surface, and the lower layer etched side surface of the metal film without the upper layer is tapered to the substrate surface. a metal gate electrode portion having a side surface shape perpendicular to the substrate surface; and a tapered side surface made of a continuous and identical metal film to the gate electrode portion. An object of the present invention is to provide a semiconductor device including a wiring portion having a shape.

[Embodiments of the invention]

FIG. 6 shows a sectional view and a plan view of a main part of a memory cell portion of an MO8 type integrated circuit in which Mo is used for word lines as an embodiment of the present invention. Note that for convenience of explanation, the passivation film and the like are omitted in the drawings for simplification. Figure 6 (
a) shows a cross-sectional view along line AA' of the Mo word line wiring portion in the plan view shown in FIG.
2 is an S1 oxide film for isolation between elements, 6 is a gate oxide film, 8 is a source region, 15 is a lower layer of l\40 wiring in the Mo word line wiring section, 16 is an upper layer of MO wiring in the Mo word line wiring section,
Reference numeral 46 indicates a lower layer portion of the Mo capacitor electrode, 44 indicates an upper layer portion of the Mo capacitor electrode, and 18 indicates an Al wiring. M.

The lower wiring portion 15 has a tapered side surface.

The Mo capacitor electrode lower layer portion 46 also has tapered side surfaces, and the Al wiring 18 can easily pass over these tapered side surfaces. Figure 6(1)) shows the I of the MO word line gate electrode portion in the plan view shown in Figure 6(C).
3B' shows a cross-sectional view along line 3B', where 1 is the 81 substrate, 2 is the S1 oxide film for element isolation, 6 is the gate oxide film, 8 is the source region, 9 is the drain region, 14 is the MO gate electrode, and 17 is the interlayer. 18 is an insulating film, 18 is an Al wiring, 43 is a lower layer of a Mo capacitor electrode, and 44 is an upper layer of a MO capacitor electrode.

The side shape of the Mo gate electrode 14 is perpendicular to the substrate surface, so that the channel length can be determined with high precision. FIG. 6(C) shows a plan view of the memory cell section. The Mo word line consists of a Mo gate electrode 14 with vertical side surfaces, an upper Mo interconnection layer 16, and a tapered lower Mo interconnection layer 1 therebelow.
5, a Mo gate electrode 14 and a Mo wiring lower layer part 1
5 consists of the same continuous Mo film. Conventionally, both the side surface of the gate electrode portion and the side surface of the wiring portion of the Mo word line are vertical or tapered. but,
In the present invention, as shown in FIG. 6(C), the side shape of one word line differs depending on the location. The functions and effects of these features will be discussed in more detail in the following section on manufacturing methods.

FIG. 4 is a diagram illustrating an embodiment of the manufacturing method of the present invention,
FIG. 2 is a cross-sectional view of a semiconductor device at key points in the manufacturing process of an MO8 type integrated circuit using MO as a word line. For convenience of explanation, the gate electrode portion and the wiring portion are shown on the same cross-sectional view. First, as shown in FIG. 4(a), an S1 oxide film 2 for element isolation is formed on the surface of the 81 substrate 10. Next, as shown in FIG. 4(b), a gate oxide film 6 is formed.

After that, on these Si oxide film 2 and gate oxide film B, a 7.5×1 [] Tor film is formed using a sputtering method.
A low oxygen concentration MO layer 10 having a film thickness of 4000× and an oxygen content of atomic % is formed in Ar gas at a pressure of r. In the embodiment of the present invention, this next step is different from the conventional method. a
Conventionally, only this low oxygen concentration MO layer 10 was used as an electrode/wiring film, and a mask material such as photoresist was directly applied onto this MO layer to form a resist pattern. However, in the embodiment of the present invention, the low oxygen concentration Mo layer 10 is deposited in the same sputtering device as the deposition susceptor, and oxygen gas is further introduced into the same device to continuously deposit the Mo film. , the oxygen content is 20 atoms
A high oxygen concentration Mo layer 11 with a film thickness of 100'A- is formed by c%. Furthermore, as shown in FIG. 4(C), a first resist turf 12 is applied to the portion that will become the wiring part of the word line.
form. Next, as shown in FIG. 4(d), using an anode-coupled parallel plate electrode type plasma etching method, the flow rate of CC1 gas was 15 scc/min, 02 in a mixed gas of CCl4 and 02. Gas flow rate 55
The high oxygen concentration Mo layer 11 is etched under the conditions of scc/exit and a pressure of 0.2 Torr, and then the first resist pattern 12 is removed.

After this, as in the conventional process, as shown in FIG. 4(e), a second resist pattern 15 is formed on both the part that will become the gate electrode part of the word line and the part that will become the wiring part. do. Thereafter, as shown in FIG. 4(f), the high oxygen concentration Mo layer 11 and the low oxygen concentration MO layer 10 are successively etched using the same parallel plate electrode type plasma etching method as described above. A Mo gate electrode 14 having a vertical side surface shape, a Mo wiring lower layer part 15 and a Mo wiring lower layer part 16 having a tapered side surface shape are formed. Thereafter, as shown in FIG. 4(g), after removing the resist pattern, using the Mo gate electrode 14 as a mask, impurity ions having a conductivity type opposite to that of the Si substrate are implanted to form the source of the MO8) transistor. A region 8 and a drain region 9 are formed, and then annealing is performed to activate the implanted impurity. Next, as shown in FIG. 4 (11), an interlayer insulating film 17 is deposited. Next, as shown in FIG. 4(i), after contact holes are opened in the interlayer insulating film 17 on the source region 8 and drain region 9, a second layer of Al wiring 18 is formed. Through the above steps, the main structures of the Mo gate electrode section and the Mo wiring section of the IVIO8 type integrated circuit can be obtained. In the example, the Mo wiring upper layer 16 is left and used as is for wiring, but as shown in FIG. 4(g)
It may be removed by the plasma etching method described above in step . In this case, the material can be selectively removed without using a mimask because of the difference in etching speed with other materials. for example,
cc14 Gas flow rate 33 scc 7h1in, 02 Gas flow rate 16SCC/min, Pressure Q, 2
Torr SRF (Radio Frequency
) Under the condition of 20 W power, high oxygen concentration MO (20a
tomic%) low oxygen concentration IVo (3atomic
%) is 2.5, '1flB
The ratio of etching rate to +oxide film 2 is 100 or more.

The first feature of the Mo word line formed in this way is:
Since the MO gate electrode 14 is composed only of the lower low oxygen concentration layer, its side surface shape is vertical. This is due to the characteristics of the parallel plate electrode type plasma etching method, which is one of the vertical etching methods. It exhibits high processing accuracy with little trenches, side etching, and small dimensional changes with respect to the resist pattern. Therefore, when used as a mask for ion implantation, the advantage is that the channel length can be controlled with high precision.

Further, since the side surfaces are vertical, leakage of implanted ions to the substrate side at the bottom portion of the gate electrode, which occurs in a tapered gate electrode, does not occur. Furthermore, in this example, since the MO film thickness of the gate electrode part is as thick as 400 OA, even if As ions with an acceleration energy of 1[]QI (eV are implanted at a dose of 4 x 1015 cm-2),
The gate electrode serving as a mask can completely block As ions within the electrode.

The second feature of the Mo word line formed according to this example is:
The side surface of the Mo wiring upper layer part 16 is formed more inward than the side surface of the Mo wiring lower layer part 15, and
The side surface of the blade is tapered. One of the reasons why such a shape is formed is that when the etching method of this example is used, as shown in FIG. and high oxygen concentration M.

The difference is that the etch rate is different for each film. Figure 5 shows
Although the flow rate ratio of 02 gas to the total gas flow rate of the mixed gas is used as a parameter, in the case of any flow rate ratio, Mo
The etch rate increases with increasing oxygen concentration in the film. Figure 6 shows the taper angle, that is, the angle formed by the side surface of the tapered Mo wiring lower layer and the underlying surface, and the high oxygen concentration M
The relationship with the oxygen concentration in the o layer is shown. However, the film thickness of the high oxygen concentration Mo layer is 1650 holes, the film thickness of the lower oxygen concentration MO layer is 16soA, and the contained oxygen concentration is 6a i
This is the case where Omi c% is closed. From this figure, the oxygen concentration in the high oxygen concentration Mo layer is 3 atomic%.
It can be seen that the taper angle can be reduced from 90 degrees to 40 degrees by increasing the angle from 90 degrees to 20 atomic %. In the MO wiring formed in this manner, the shape of the ff15 interlayer insulating film 17 on the side surface of the Mo wiring also exhibits approximately the same taper angle reflecting the taper shape of the side surface of the Mo wiring.

Therefore, the Al wiring 18 formed on the interlayer insulating film 17 can also cover the side surface of the Mo wiring with a taper angle reflecting the surface shape of the underlying interlayer insulating film 17. This allows the MO with vertical sides to
Compared to the case where the wiring is covered, the probability of disconnection of the Al wiring on the side surface of the Mo wiring and phenomena such as increased resistance and short circuit of the Al wiring even if disconnection occurs are significantly improved. Further, the film thickness of the MO wiring can be increased compared to the conventional method without causing the above-mentioned disconnection, etc., which has the advantage of reducing the resistance of the wiring and speeding up the operation of the circuit.

As explained in the above embodiments, MO to which the present invention is applied
In Mo word lines of 8-inch integrated circuits, the sides of the gate electrode part can be made vertical, which has an advantage in the performance of MO8) transistors, and at the same time, the sides of the wiring part can be made tapered, so multilayer This has advantages in the performance of intersections when wiring.

In this example, the word line of an MO8 type integrated circuit is shown, but it is also applicable to a semiconductor device that requires two types of side shapes, vertical and tapered, in the same metal film surface as electrodes and wiring. and for its manufacture, M.
It is applicable without being limited to OS type or Si semiconductors. In addition, in this example, Mo is used as the electrode/wiring metal.
We used an anode-coupled parallel plate electrode plasma etching method as the etching method, but if we use a combination of a metal and etching method that increases the etch rate by adding oxygen into the film, it is possible to use other etching methods. Even if a metal and an etching method are used, the present invention can be applied in the same manner as in the embodiment. When a parallel plate electrode type plasma etching method is used, it is possible to obtain the same effect as in the embodiment even if W or Cr is used in addition to MO.

Although the electrode pattern and wiring pattern have been described above, the advantages of forming vertical side surfaces can also be applied to overlapping alignment mark patterns.

As is well known, in the IC manufacturing process, multiple layers are formed, from element isolation pattern formation to wiring pattern formation (in the case of a single-layer gate structure, element isolation, gate electrode, through hole, and wiring pattern formation). It is formed at a predetermined position relative to the formed pattern. For this,
Usually, an overlay alignment mark pattern necessary for forming a resist pattern in the next layer is formed and left on each layer.

As alignment accuracy (allowable positional deviation dimension) becomes stricter as elements become smaller, control of the shape of overlapping alignment patterns is important. That is, if the overlapping alignment pattern has a tapered side surface, the sharpness of the pattern edge line will be lost, making it difficult to accurately position the alignment pattern when forming the next layer pattern. For example, when forming a resist pattern using ultraviolet exposure, the side surfaces of the grooves become tapered, making accurate alignment difficult because the pattern edges cannot be clearly identified. When a mark is detected by electron scanning irradiation on a pattern, pattern edge detection becomes inaccurate due to electron scattering at a portion of the taper, resulting in a large error in overlapping positioning. On the other hand, in the present invention, as in the case of the above-described embodiment, the resist is removed in the overlapping position alignment notch turn area (not shown) in the step shown in FIG. 4(C). If this is done, an alignment mark pattern with vertical side surfaces without a taper as shown in FIG. 4(f) can be obtained, and problems in overlapping alignment can be eliminated.

〔Effect of the invention〕

As explained above, according to the present invention, the oxygen concentration in the upper layer is lower than that in the lower layer, compared to the conventional method in which the side shapes of metal electrodes and wiring in a semiconductor device are both vertical or tapered. A vertical gate electrode and a tapered wiring are formed by depositing a two-under-two-layer structure metal film, removing the upper layer of this metal film in advance from the part that will become the gate electrode, and then patterning the electrode and wiring. Same as -
This makes it possible to form the tapered side surface shape of the wiring part at the same time in the film surface, and the tapered side surface shape of the wiring part is similar to that of the second layer wiring formed by sandwiching an interlayer insulating film on top of the wiring. This has the effect of significantly alleviating the disconnection and resistance increase that occur at the portion of the wiring that crosses the step on the side surface of the wiring.Also, the vertical side surface shape of the gate electrode part that is formed at the same time allows the electrode to maintain the tapered shape of the wiring part. It is possible to define the line width with high precision, and in cases where the MO8 electrode is used as a mask for ion implantation for source/drain formation, the channel length can be controlled with high precision.

[Brief explanation of drawings]

1 and 2 are enlarged sectional views of main parts of a semiconductor device to explain the conventional manufacturing process of electrodes and wiring, and FIG. 6 is a main part of a memory cell part to explain a semiconductor device according to the present invention. 4 is an enlarged sectional view of a main part of a semiconductor device to explain the manufacturing process of electrodes and wiring according to the present invention, and FIG. 5 is a diagram showing the relationship between oxygen concentration and etch rate in the Mo film. FIG. 6 is a characteristic diagram showing the relationship between the oxygen concentration of the high oxygen concentration Mo layer and the taper angle. Explanation of symbols 1 Si substrate 2 8i oxide film for element isolation 6 Mo thin film 4 Resist pattern 5 N10 word line wiring section 6 Gate oxide film 7 Tapered shape MO gate electrode 8 Source region 9...Drain region 10...
Low oxygen concentration Mo layer 11... High oxygen concentration Mo layer 12.
First resist pattern 1ro... Second resist pattern 14... Mo cathode electrode 15... Mo interconnect lower layer portion 16... IVo interconnect upper layer portion 17... Interlayer insulating film 18
...Al wiring 41...Resist pattern 4 with tapered side surfaces
2. Thin resist pattern 46... Mo capacitor electrode lower layer 44 Mo capacitor electrode upper layer W1... Resist pattern width W2... Gate electrode width Patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation 1F1 diagram? Figure 2? j! :1 year old 4 figure 1P6 figure high acid level No layer/l! Ship change degree (衾6柘C%) -1'
S

Claims (2)

[Claims] (1) In a semiconductor device including a gate electrode serving as a signal input terminal and a wiring serving as a connection line for applying voltage from a power source to the gate electrode, a metal gate electrode portion having a side surface perpendicular to the substrate surface; 1. A semiconductor device comprising: a wiring portion continuous with the metal gate electrode portion and having a tapered side surface made of the same metal film. (2) In a method for manufacturing a semiconductor device that includes a gate electrode that serves as a signal input terminal and a wiring that serves as a connection line for applying voltage from a power source to the gate electrode, the upper and lower layers have a higher oxygen concentration in the upper layer than the lower layer. The process of forming a structural metal film on the substrate, and performing the first patterning only on this upper layer to cover only the upper layer covering the gate electrode part? a step of removing the gate electrode, and a step of performing a second patterning that reaches the lower metal film over the entire surface after this step to form a gate electrode having a 10,000-sided shape perpendicular to the substrate surface and a wiring having a tapered lateral shape. A semiconductor device manufacturing method comprising: