JPS62224946A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPS62224946A JPS62224946A JP6732086A JP6732086A JPS62224946A JP S62224946 A JPS62224946 A JP S62224946A JP 6732086 A JP6732086 A JP 6732086A JP 6732086 A JP6732086 A JP 6732086A JP S62224946 A JPS62224946 A JP S62224946A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- single crystal
- semiconductor
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 10
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 230000002146 bilateral effect Effects 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Landscapes
- Processing Of Stones Or Stones Resemblance Materials (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、異なる複数の半導体層で構成される半導体
基体の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor substrate composed of a plurality of different semiconductor layers.
(従来の技術)
従来、この種のエピタキシャル成長用半導体基板は、シ
リコン(以下Siという)基板やガリウム砒素(以下G
aAsという)基板等が用いられ、Sl基板にはSi、
GaAs基板にはGaAaという組合せで、同種または
極めて近い種類、例えばGaAs基板にGaAAAsと
いう組合せで、エピタキシャル成長が行われていた。ま
た、最近の有機金属化学気相成長(以下MOCVDとい
う)法または分子線エピタキシャル成長(以下MBEと
いう)法を使うことによって、Si基板やダルマニウム
基板の上にGaAsという全く熱的性質も結晶格子定数
も異なる異質な材料の組合せによるいわゆるヘテロエビ
タギシー成長が文献、日経マイクロデバイス(1,98
6年1月号)P、P、 113−127等に記載されて
いる方法により可能となってきた。(Prior Art) Conventionally, this type of semiconductor substrate for epitaxial growth has been made of a silicon (hereinafter referred to as Si) substrate or a gallium arsenide (hereinafter referred to as G) substrate.
aAs) substrate etc. are used, and the Sl substrate is made of Si,
Epitaxial growth has been performed on a GaAs substrate using a combination of GaAAa, and using the same type or a very similar type, for example, a combination of GaAAAs on a GaAs substrate. Furthermore, by using the recent metal organic chemical vapor deposition (hereinafter referred to as MOCVD) method or molecular beam epitaxial growth (hereinafter referred to as MBE) method, it is possible to deposit completely thermal properties of GaAs on a Si substrate or damanium substrate with a crystal lattice constant. The so-called heteroepitactic growth due to the combination of different and different materials has been reported in the literature, Nikkei Microdevices (1,98
This has been made possible by the method described in P, P, 113-127, etc.
(発明が解決しようとする問題点)
しかしながら、以上述べたような従来の方法では、例え
ば2インチのSi基板にGaAs層を3μm〜411m
厚さにMOCVD (有機金属化学気相成長)法捷たは
MBE (分子線エピタキシャル成長)法により積層す
ると、GaAs面を内側に基板が50μm〜60μm反
り、さらに厚く成長させるとクラックが生じ、LSIや
高周波デバイスなど微細なパターンを形成するときに問
題となる。(Problems to be Solved by the Invention) However, in the conventional method as described above, for example, a GaAs layer is formed on a 2-inch Si substrate with a thickness of 3 μm to 411 μm.
When laminated to a certain thickness using MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxial growth), the substrate warps by 50 to 60 μm with the GaAs surface inward, and if it is grown even thicker, cracks occur, causing problems such as LSI and This becomes a problem when forming fine patterns such as in high-frequency devices.
この発明の目的は以上述べたエピタキシャル成長により
積層するGaAs等の層の厚さの限界をなくし、Si基
板上へのGaAsの成長のような異質の物質をエピタキ
シャル成長するヘテロエピタキシャル成長における熱的
性質の違いによる厚さの制限をなくすことにある。また
4インチ、5インチの大型Si基板にもヘテロエピタキ
シャル成長を可能とすることを目的とする。The purpose of this invention is to eliminate the limit on the thickness of layers such as GaAs that are stacked by epitaxial growth as described above, and to avoid the difference in thermal properties in heteroepitaxial growth in which a different material, such as GaAs, is grown on a Si substrate. The goal is to eliminate thickness restrictions. Another purpose is to enable heteroepitaxial growth on large Si substrates of 4 inches and 5 inches.
(問題点を解決するための手段)
この発明は前記問題点を解決するために、半導体基板の
表面に、この半導体基板のオリエンテーションフラット
面に平行および垂直であって、且つ、ダイスの大きさに
対応した間隔あるいは5〜10TIrmの所定間隔を有
した複数の溝を形成したのち、この半導体基板の表面に
この半導体基板とは異なる材料の化合物半導体単結晶層
を積層するものである。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a structure in which the surface of the semiconductor substrate is parallel to and perpendicular to the orientation flat surface of the semiconductor substrate, and is parallel to and perpendicular to the size of the die. After forming a plurality of grooves with corresponding intervals or predetermined intervals of 5 to 10 TIrm, a compound semiconductor single crystal layer made of a material different from that of the semiconductor substrate is laminated on the surface of the semiconductor substrate.
(作用)
この発明によれば、以上説明したように半導体基板の表
面に複数の溝を形成しているので、この半導体基板の表
面にこの半導体基板とは異なる材料の化合物半導体単結
晶層を成長させると成長面に対して凹形に反りが生じる
が、この半導体基体を用いて化合物半導体単結晶層にL
SI等の半導体装置を形成する際、物理的な力を加えて
平坦に変形しても、細い溝の内部にのみ確実にクラック
が入り、この半導体装置に悪影響を及ぼすクラックが生
じることはない。(Function) According to the present invention, as described above, since a plurality of grooves are formed on the surface of the semiconductor substrate, a compound semiconductor single crystal layer made of a material different from that of the semiconductor substrate is grown on the surface of the semiconductor substrate. However, when this semiconductor substrate is used to form a compound semiconductor single crystal layer, L
When forming a semiconductor device such as an SI, even if a physical force is applied to deform the device into a flat shape, cracks will surely form only inside the narrow grooves, and no cracks will have a negative impact on the semiconductor device.
(実施例)
第1図はこの発明の実施例を示すエピタキシャル成長用
基板1の表面を示す図であり、第2図及び第3図はその
断面拡大図である。以下、図面に沿って説明する。(Example) FIG. 1 is a view showing the surface of an epitaxial growth substrate 1 showing an example of the present invention, and FIGS. 2 and 3 are enlarged cross-sectional views thereof. The explanation will be given below along with the drawings.
まず第1図に示すように、エピタキシャル成長用基板1
0表面に細い溝2(第2図参照)をオリエンテーション
フラット面3に平行、垂直に加工する。例えば2インチ
5t(100)基板をエピタキシャル基板1として用い
る時には通常基板の厚みは200μm〜250μmであ
シ、細い溝加工は、100〜150μm深さにエツチン
グまたはダイシングソーによシ行う。3インチや4イン
チの大口径の基板については残りの厚みが100μm〜
150μmで溝加工を行う。縦横の溝2は左右上下対称
が好ましく、且つその間隔は、このエピタキシャル成長
用基板1をダイシングする際のダイスの大きさに対応し
た間隔に形成する。ダイスが10Trr!n口よシ大き
い時には、5〜1011mの所定間隔で形成する。また
、溝の幅は狭くて十分で、例えばダイシングソーで溝加
工する場合には20μm程度の幅の刃を使って加工する
。First, as shown in FIG. 1, an epitaxial growth substrate 1 is prepared.
A thin groove 2 (see Fig. 2) is machined on the 0 surface parallel to and perpendicular to the orientation flat surface 3. For example, when a 2-inch 5t (100) substrate is used as the epitaxial substrate 1, the thickness of the substrate is usually 200 to 250 μm, and the narrow grooves are formed by etching or dicing saw to a depth of 100 to 150 μm. For large diameter boards of 3 inches or 4 inches, the remaining thickness is 100 μm or more.
Grooving is performed at 150 μm. The vertical and horizontal grooves 2 are preferably horizontally and vertically symmetrical, and their intervals are formed at intervals corresponding to the size of the dice when this epitaxial growth substrate 1 is diced. The dice are 10Trr! When the distance is larger than n, it is formed at a predetermined interval of 5 to 1011 m. Further, the width of the groove is sufficient if it is narrow; for example, when cutting the groove with a dicing saw, a blade with a width of about 20 μm is used.
次に第2図に示すように、エピタキシャル成長用基板1
の細い溝2の加工をした面に直接あるいはバッファ層を
介して、MOCVD法あるいはMBE法により異質な単
結晶層4を成長させることにより半導体基体を製造する
。Next, as shown in FIG. 2, an epitaxial growth substrate 1 is formed.
A semiconductor substrate is manufactured by growing a heterogeneous single crystal layer 4 by MOCVD or MBE directly or through a buffer layer on the surface where the narrow grooves 2 have been processed.
例えばエピタキシャル成長用基板1として前記Si基板
を用いる時には、約900℃でSi基板1を熱処理する
ことによシ表面を清浄にし、次にMOCVD法ならば4
00〜450℃、MBE法ならば150〜400℃の低
い温度で厚さ20nm(らいのGaAsを堆積させ、成
長をいったん中断してから基板温度を700〜750℃
に上げ2回目の成長を行うことにより GaAs単結晶
層を成長させる。For example, when using the Si substrate 1 as the substrate 1 for epitaxial growth, the surface of the Si substrate 1 is cleaned by heat-treating it at about 900° C., and then if MOCVD is used,
00 to 450°C; in the case of the MBE method, 20 nm thick GaAs is deposited at a low temperature of 150 to 400°C, the growth is interrupted once, and the substrate temperature is increased to 700 to 750°C.
By increasing the temperature and performing a second growth, a GaAs single crystal layer is grown.
本発明の実施例では、以」二のようにSi基板の上にM
OCVD法やMBE法により GaAs単結晶層を3〜
4μm成長すると50μm程凹形に変形し、さらに、本
発明の実施例ではエピタキシャル成長用基板、1の表面
に細い溝2を形成しているため、厚くヘテロエピタキシ
ャル成長を行えば行うほど成長面に対する凹形の変形の
度合は膜厚に比例して大きくなり、細い溝2がないと2
インチのシリコン基板の上にGaAgを5μm以上成長
するとクラックが入り半導体装置を製作するための半導
体基体として使うことは不可能であるが、細い溝2を設
けることによりエピタキシャル成長用基板lは大きく変
形するが、単結晶層4の成長時におけるクラックの発生
はなく、また、半導体装置の製造過程で密着露光等にお
いて物理的な力で平坦に変形しても、GaASの単結晶
層はSiのエピタキシャル成長用基板lに比較してヘキ
カイしやすい材料であるため、第3図に示すように細い
溝2の内部にのみ確実にクラック5が入り、平らな半導
体基体となる。従って、後工程の密着露光等でもl・ラ
ブルは発生しない。In the embodiment of the present invention, M
Three to three GaAs single crystal layers are formed by OCVD method or MBE method.
When it grows by 4 μm, it deforms into a concave shape by about 50 μm. Furthermore, in the embodiment of the present invention, since thin grooves 2 are formed on the surface of the epitaxial growth substrate 1, the thicker the heteroepitaxial growth is performed, the more concave the growth surface becomes. The degree of deformation increases in proportion to the film thickness, and if there is no thin groove 2,
If GaAg is grown to a thickness of 5 μm or more on an inch-inch silicon substrate, it will crack and cannot be used as a semiconductor substrate for manufacturing semiconductor devices, but by providing the thin groove 2, the epitaxial growth substrate l will be greatly deformed. However, no cracks occur during the growth of the single crystal layer 4, and even if it is deformed flat due to physical force during contact exposure during the manufacturing process of semiconductor devices, the single crystal layer of GaAS is suitable for epitaxial growth of Si. Since the material is more susceptible to cracking than the substrate 1, cracks 5 will surely form only inside the narrow grooves 2, as shown in FIG. 3, resulting in a flat semiconductor substrate. Therefore, l-rubble does not occur even during close contact exposure in the subsequent process.
また、溝2はダイスの大きさに対応した間隔で形成して
いるので、このように形成した半導体基体に形成される
半導体装置への悪影響はない。Moreover, since the grooves 2 are formed at intervals corresponding to the size of the die, there is no adverse effect on the semiconductor device formed on the semiconductor substrate thus formed.
(発明の効果)
この発明によれば、以上詳細に説明したように半導体基
板の表面に互いに直交する溝を形成し、この表面にこの
半導体基板と異なる材料の化合物半導体単結晶層を成長
させているので、半導体基板にクラックが生じても、こ
の単結晶層に形成されるLSIや高周波デバイス等の半
導体装置に悪影響を与えることはなく、厚い化合物半導
体単結晶層を有し且つ大口径の半導体基体を製造するこ
とができる。(Effects of the Invention) According to the present invention, as described in detail above, grooves perpendicular to each other are formed on the surface of a semiconductor substrate, and a compound semiconductor single crystal layer made of a material different from that of the semiconductor substrate is grown on this surface. Therefore, even if a crack occurs in the semiconductor substrate, it will not have an adverse effect on semiconductor devices such as LSIs and high frequency devices formed on this single crystal layer. A substrate can be manufactured.
第1図は本発明の実施例を示すエピタキシャル成長用の
基板を表面から見た平面図であり、第2図は化合物半導
体単結晶層を成長させたときの基板の断面拡大図であり
、第3図は基板を平坦にしたときの溝部分の断面拡大図
である。
1・・・基板、2・・・溝、3・・・オリエンテーショ
ンフラット面、4・・・単結晶層、5・・・クラック。FIG. 1 is a plan view of a substrate for epitaxial growth showing an embodiment of the present invention viewed from the surface, FIG. 2 is an enlarged cross-sectional view of the substrate when a compound semiconductor single crystal layer is grown, and FIG. The figure is an enlarged cross-sectional view of the groove portion when the substrate is flattened. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Groove, 3...Orientation flat surface, 4...Single crystal layer, 5...Crack.
Claims (1)
ョンフラット面に平行および垂直であって且つ所定の間
隔を有した複数の溝を形成する工程と、 該半導体基板の表面に該半導体基板とは異なる材料の化
合物半導体単結晶層を積層する工程とを備えてなること
を特徴とする半導体基体の製造方法。 2、前記所定の間隔をダイスの大きさに対応した間隔と
することを特徴とする特許請求の範囲第1項記載の半導
体基体の製造方法。 3、前記所定の間隔を5〜10mmの間隔とすることを
特徴とする特許請求の範囲第1項記載の半導体基体の製
造方法。[Claims] 1. Forming a plurality of grooves on the surface of the semiconductor substrate parallel and perpendicular to the orientation flat surface of the semiconductor substrate and having predetermined intervals; 1. A method for manufacturing a semiconductor substrate, comprising the step of laminating compound semiconductor single crystal layers made of a material different from that of the semiconductor substrate. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the predetermined interval is an interval corresponding to the size of the die. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the predetermined interval is 5 to 10 mm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61067320A JPH0722122B2 (en) | 1986-03-27 | 1986-03-27 | Method for manufacturing semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61067320A JPH0722122B2 (en) | 1986-03-27 | 1986-03-27 | Method for manufacturing semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62224946A true JPS62224946A (en) | 1987-10-02 |
JPH0722122B2 JPH0722122B2 (en) | 1995-03-08 |
Family
ID=13341607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61067320A Expired - Fee Related JPH0722122B2 (en) | 1986-03-27 | 1986-03-27 | Method for manufacturing semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0722122B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01107515A (en) * | 1987-10-20 | 1989-04-25 | Daido Steel Co Ltd | Manufacture of semiconductor element |
JPH0529454A (en) * | 1991-07-19 | 1993-02-05 | Seikosha Co Ltd | Manufacture of semiconductor integrated circuit chip |
WO2001063654A3 (en) * | 2000-02-24 | 2002-02-07 | Univ North Carolina State | Methods of forming a plurality of semiconductor layers using trench arrays |
US6897126B2 (en) * | 2001-07-09 | 2005-05-24 | Sanyo Electric, Co., Ltd. | Semiconductor device manufacturing method using mask slanting from orientation flat |
JP2009249190A (en) * | 2008-04-01 | 2009-10-29 | Mitsumi Electric Co Ltd | Manufacturing method of carbon nanotube |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60106124A (en) * | 1983-11-14 | 1985-06-11 | Hitachi Ltd | Formation of semiconductor thin film on insulating substrate |
-
1986
- 1986-03-27 JP JP61067320A patent/JPH0722122B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60106124A (en) * | 1983-11-14 | 1985-06-11 | Hitachi Ltd | Formation of semiconductor thin film on insulating substrate |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01107515A (en) * | 1987-10-20 | 1989-04-25 | Daido Steel Co Ltd | Manufacture of semiconductor element |
JPH0529454A (en) * | 1991-07-19 | 1993-02-05 | Seikosha Co Ltd | Manufacture of semiconductor integrated circuit chip |
WO2001063654A3 (en) * | 2000-02-24 | 2002-02-07 | Univ North Carolina State | Methods of forming a plurality of semiconductor layers using trench arrays |
US6897126B2 (en) * | 2001-07-09 | 2005-05-24 | Sanyo Electric, Co., Ltd. | Semiconductor device manufacturing method using mask slanting from orientation flat |
CN100466170C (en) * | 2001-07-09 | 2009-03-04 | 三洋电机株式会社 | Method for making compound semiconductor device |
JP2009249190A (en) * | 2008-04-01 | 2009-10-29 | Mitsumi Electric Co Ltd | Manufacturing method of carbon nanotube |
Also Published As
Publication number | Publication date |
---|---|
JPH0722122B2 (en) | 1995-03-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |