JPH03191549A - Manufacture of compound semiconductor device on si substrate - Google Patents
Manufacture of compound semiconductor device on si substrateInfo
- Publication number
- JPH03191549A JPH03191549A JP1332226A JP33222689A JPH03191549A JP H03191549 A JPH03191549 A JP H03191549A JP 1332226 A JP1332226 A JP 1332226A JP 33222689 A JP33222689 A JP 33222689A JP H03191549 A JPH03191549 A JP H03191549A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- grooves
- gaas
- compound semiconductor
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 150000001875 compounds Chemical class 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 26
- 230000012010 growth Effects 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Dicing (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はＳｉ基板上化合物半導体装置の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a compound semiconductor device on a Si substrate.
第３図は例えば従来のＳｉ基板上ＧａＡｓ太陽電池の製
造方法を示す断面図である０図において、１はＳｉ基板
、２はＧａＡｓバッファ層、３はＧａＡｓ能動層、４は
表面電極、５は裏面電極である。FIG. 3 is a cross-sectional view showing, for example, a conventional method for manufacturing a GaAs solar cell on a Si substrate. In FIG. 0, 1 is a Si substrate, 2 is a GaAs buffer layer, 3 is a GaAs active layer, 4 is a surface electrode, and 5 is a This is the back electrode.
次に製造方法を第３図■〜■に従って説明する。Next, the manufacturing method will be explained according to FIGS.
■ 化学処理されたＳｉ基板１上にＧａＡｓバッファ層
２をＭＯＣＶＤ法等の方法により成長する。(2) A GaAs buffer layer 2 is grown on the chemically treated Si substrate 1 by a method such as MOCVD.
■ メサエッチングによりＧａＡｓバッファ層２の分離
を行う。(2) Separate the GaAs buffer layer 2 by mesa etching.
■ 分離されたＧａＡｓバッファ層２上に選択的にＧａ
Ａｓ活性層３をエピタキシャル成長させる。■ Selectively deposit Ga on the separated GaAs buffer layer 2
The As active layer 3 is epitaxially grown.
■ ＧａＡｓ活性層３上に表面電極４を形成する。(2) A surface electrode 4 is formed on the GaAs active layer 3.
■ Ｓｉ基板１を裏面研磨又は裏面エツチング工程によ
り薄型化を行う。(2) The thickness of the Si substrate 1 is reduced by polishing or etching the back surface.
■ Ｓｉ基板１の裏面に裏面電極５の形成を行う。(2) A back electrode 5 is formed on the back surface of the Si substrate 1.
■ ダイシングにより素子分離を行う。■ Element separation is performed by dicing.
このような製造方法により形成されたデバイスにおいて
、各工程における歩留まりの低下状況を第２図（ａ）に
示す。FIG. 2(a) shows how the yield decreases in each step in a device formed by such a manufacturing method.
従来の製造プロセスは以上の様に構成されているため、
第３図■と■の工程で合計２回もエピタキシャル成長を
行う必要がある。また、このような２回のエピタキシャ
ル成長の間のフォトリソグラフィー工程及びエツチング
工程（第３図■）では、素子の表面が汚染されることが
多く、これにより活性層のＧａＡｓの品質が劣化してし
まい、歩留まりの低下が生じていた。さらには第３図■
〜■に示すように基板１を薄型化して機械的強度の弱く
なったウェハに裏面電極形成、ダイシングの工程を行う
必要があるので、ウェハ割れ、チップ欠は等が生じやす
く歩留り低下が避けられない等の問題があった。Since the conventional manufacturing process is structured as described above,
It is necessary to perform epitaxial growth a total of two times in the steps (■) and (■) in FIG. 3. Furthermore, in the photolithography process and etching process (Fig. 3 ■) between two epitaxial growths, the surface of the device is often contaminated, which deteriorates the quality of the GaAs in the active layer. , a decrease in yield occurred. Furthermore, Figure 3■
As shown in ~■, it is necessary to perform back electrode formation and dicing processes on a wafer whose mechanical strength has been weakened by thinning the substrate 1, so that wafer cracking, chipping, etc. are likely to occur, and a decrease in yield can be avoided. There were problems such as not having one.
この発明は、上記の様な問題点を解消するためになされ
たもので、メサエッチング工程、基板薄型化後のダイシ
ングカット工程をなくすことができるとともに、薄いＳ
ｉ基板上に形成されたＧａＡｓデバイスチップを容易に
高歩留りで得ることができるＳｉ基板上化合物半導体装
置の製造方法を提供することを目的とする。This invention was made to solve the above-mentioned problems, and it is possible to eliminate the mesa etching process and the dicing cut process after thinning the substrate, and also to
An object of the present invention is to provide a method for manufacturing a compound semiconductor device on a Si substrate, which allows GaAs device chips formed on an i-substrate to be easily obtained at a high yield.
この発明に係るＳｉ基板上化合物半導体装置の製造方法
は、Ｓｉ基板の表面に碁盤目状に所望の深さの溝を形成
し、基板上の溝以外の部分にＧａＡｓＩＩの成長を行い
、次いでＳｉ基板を裏面側から基板が溝の深さ以下の厚
みになる迄、研磨又はエツチングすることにより素子分
離を行うようにしたものである。In the method for manufacturing a compound semiconductor device on a Si substrate according to the present invention, grooves of a desired depth are formed in a checkerboard pattern on the surface of a Si substrate, GaAsII is grown on a portion of the substrate other than the grooves, and then Si Element isolation is performed by polishing or etching the substrate from the back side until the thickness of the substrate is equal to or less than the depth of the groove.
この発明におけるＳｉ基板上化合物半導体装置の製造方
法では、ＧａＡｓバッファ層のメサエッチング工程、及
び基板薄型化後のダイシング工程をなくすことができ、
エピタキシャル成長を連続して行えるとともに、素子分
離と基板の薄膜化が同時に行える。In the method of manufacturing a compound semiconductor device on a Si substrate according to the present invention, the mesa etching process of the GaAs buffer layer and the dicing process after thinning the substrate can be eliminated,
Epitaxial growth can be performed continuously, and element isolation and substrate thinning can be performed simultaneously.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図■〜■はこの発明の一実施例によるＳｉ基板上半
導体装置の製造方法を示す各主要工程の断面構造を示す
図である０図において、１はＳｉ基板、１１はＳｉ基板
１の表面に形成された溝、２はＧａＡｓバフファ層、３
はＧａＡｓ能動層、４は表面電極、５は裏面電極である
。Figures 1 to 1 are diagrams showing the cross-sectional structure of each main step of a method for manufacturing a semiconductor device on a Si substrate according to an embodiment of the present invention. In Figure 0, 1 is a Si substrate; Grooves formed on the surface, 2 are GaAs buffer layers, 3
is a GaAs active layer, 4 is a front electrode, and 5 is a back electrode.
次に製造方法について図に従って説明する。Next, the manufacturing method will be explained according to the drawings.
■ Ｓｉ基板１表面に深さが５０〜２００μｍ程度の溝
１１を碁盤目状に形成し、化学処理を行う。(2) Grooves 11 having a depth of approximately 50 to 200 μm are formed in a checkerboard pattern on the surface of the Si substrate 1, and chemical treatment is performed.
■ このように形成した基板上の溝１１形成部以外のと
ころに選択的に、ＧａＡｓバッファＮ２゜ＧａＡｓ能動
層３を順次エピタキシャル成長させる。(2) A GaAs buffer N2°GaAs active layer 3 is sequentially epitaxially grown selectively on the substrate formed in this manner in areas other than the groove 11 forming portion.
■ ＧａＡｓ能動層上に表面電極４を形成する。(2) A surface electrode 4 is formed on the GaAs active layer.
■ Ｓｉ基板１を裏面側から溝１１の深さ（５０〜２０
０μｍ程度）以下の厚みになる迄、研磨又はエツチング
する。この工程により、基板の薄型化と太陽電池セルの
分離が同時に行える。■ Depth the groove 11 from the back side of the Si substrate 1 (50 to 20
Polish or etch until the thickness is less than 0 μm. This process allows the substrate to be thinned and the solar cells to be separated at the same time.
■ この状態でｓｉ基板の裏面に裏面電極を形成して本
装置を完成する。(2) In this state, a back electrode is formed on the back surface of the Si substrate to complete the device.
以上、Ｓｉ基板上化合物半導体装置の各工程における歩
留り状況を第２図（ｂ）に示す。本実施例の製造方法に
よれば、従来のＧａＡｓバッファ層のメサエッチング工
程をなくすようにしたので、基板１上にＧａＡｓバッフ
ァ層２ ＋ Ｇ ａ Ａ ｓ能動層３を連続してエピタ
キシャル成長させることができ、結晶成長工程での歩留
まり及び結晶性の劣化を防止できる。また、さらには基
板薄型化後のダイシング工程を省略できるので、さらに
歩留まりの低下を防止できる。The yield status in each process of the compound semiconductor device on a Si substrate is shown in FIG. 2(b). According to the manufacturing method of this embodiment, since the conventional mesa etching process for the GaAs buffer layer is eliminated, it is possible to epitaxially grow the GaAs buffer layer 2 + GaAs active layer 3 on the substrate 1 in succession. This makes it possible to prevent deterioration of yield and crystallinity in the crystal growth process. Furthermore, since the dicing step after thinning the substrate can be omitted, it is possible to further prevent a decrease in yield.
なお、上記実施例はＳｉ基板上ＧａＡｓ太陽電池の製造
工程について示したが、半導体装置としてはフォトダイ
オード、ＬＥＤ、レーザ等の任意の光デバイスであって
もよく、また、これはＦＥＴの様な電子デバイスであっ
てもよい。Although the above embodiment describes the manufacturing process of a GaAs solar cell on a Si substrate, the semiconductor device may be any optical device such as a photodiode, LED, or laser. It may also be an electronic device.
また、Ｓ）基板ｌ上に成長される化合物半導体結晶は、
ＧａＡｓに限らず、ＩｎＰ、ＧａＰやこれらの混晶であ
ってもよく、これらの場合においても上記実施例と同等
の効果を奏する。Also, S) the compound semiconductor crystal grown on the substrate l is
The material is not limited to GaAs, but may be InP, GaP, or a mixed crystal thereof, and even in these cases, the same effect as in the above embodiment can be achieved.
以上のようにこの発明によれば、基板としてＳｉ表面に
碁盤目状に５０μｍ〜２００μｍ程度の深さの溝を形成
し、この溝形成部以外の基板上に選択的に化合物半導体
からなるバッファ層、能動層のエピタキシャル成長を行
い、次いでＳｉ基板を裏面側から基板が溝の深さ以下の
厚みになる迄研磨又はエツチングすることにより基板の
薄型化及び素子分離を行うようにしたので、従来の化合
物半導体層のメサエソチング工程を失くすることができ
、工程が簡略化されると共に、化合物半導体層のエピタ
キシャル成長を連続して行えるため、結晶成長工程での
歩留り及び結晶性の劣化を防止出来る効果がある。また
、従来の基板薄型化後のダイシング工程をなくすことが
できるので、薄い基板上に形成されたＳｉ基板上化合物
半導体装置を高い歩留りで得られる効果がある。As described above, according to the present invention, grooves having a depth of about 50 μm to 200 μm are formed in a checkerboard pattern on the Si surface as a substrate, and a buffer layer made of a compound semiconductor is selectively formed on the substrate other than the groove forming portions. , the active layer is epitaxially grown, and then the Si substrate is polished or etched from the back side until the thickness of the substrate is less than the depth of the groove, thereby thinning the substrate and separating the elements, which is easier than using conventional compounds. It is possible to eliminate the mesa etching process of the semiconductor layer, which simplifies the process, and allows continuous epitaxial growth of the compound semiconductor layer, which has the effect of preventing deterioration of yield and crystallinity in the crystal growth process. . Furthermore, since the conventional dicing process after thinning the substrate can be eliminated, there is an effect that a compound semiconductor device on a Si substrate formed on a thin substrate can be obtained at a high yield.
第１図はこの発明の一実施例によるＳｉ基板上化合物半
導体装置の製造方法による製造工程の流れを示す断面側
面図、第２図は従来の工程及び本発明による工程の工程
歩留りを示す図、第３図は従来のＳｉ基板上化合物半導
体装置の製造方法の工程の流れを示す断面側面図である
。
１は８１基板、２は化合物半導体バッファ層、３は化合
物半導体能動層、４は表面電極、５は裏面電極、１１は
Ｓｉ基板に形成された溝である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional side view showing the flow of the manufacturing process according to the method for manufacturing a compound semiconductor device on a Si substrate according to an embodiment of the present invention, and FIG. 2 is a diagram showing the process yield of the conventional process and the process according to the present invention. FIG. 3 is a cross-sectional side view showing the process flow of a conventional method for manufacturing a compound semiconductor device on a Si substrate. 1 is an 81 substrate, 2 is a compound semiconductor buffer layer, 3 is a compound semiconductor active layer, 4 is a front electrode, 5 is a back electrode, and 11 is a groove formed in the Si substrate. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
さを有する溝を形成する工程と、 該Ｓｉ基板表面の溝形成部以外の部分に化合物半導体層
を形成する工程と、 上記Ｓｉ基板が溝の深さ以下の厚みになるまで該Ｓｉ基
板をその裏面側からエッチングあるいは研磨して素子分
離を行う工程とを含むことを特徴とするＳｉ基板上化合
物半導体装置の製造方法。(1) A step of forming grooves having a desired depth arranged in a checkerboard pattern on the surface of the Si substrate, and a step of forming a compound semiconductor layer on a portion of the surface of the Si substrate other than the groove forming portion; 1. A method for manufacturing a compound semiconductor device on a Si substrate, comprising the step of etching or polishing the Si substrate from the back side until the thickness of the Si substrate becomes equal to or less than the depth of the groove to separate elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332226A JPH03191549A (en) | 1989-12-20 | 1989-12-20 | Manufacture of compound semiconductor device on si substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1332226A JPH03191549A (en) | 1989-12-20 | 1989-12-20 | Manufacture of compound semiconductor device on si substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03191549A true JPH03191549A (en) | 1991-08-21 |
Family
ID=18252584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1332226A Pending JPH03191549A (en) | 1989-12-20 | 1989-12-20 | Manufacture of compound semiconductor device on si substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03191549A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184109B1 (en) | 1997-07-23 | 2001-02-06 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
| US6294439B1 (en) | 1997-07-23 | 2001-09-25 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
| US6337258B1 (en) | 1999-07-22 | 2002-01-08 | Kabushiki Kaisha Toshiba | Method of dividing a wafer |
| JP2004327708A (en) * | 2003-04-24 | 2004-11-18 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2005166913A (en) * | 2003-12-02 | 2005-06-23 | Sharp Corp | Manufacturing method of compound semiconductor solar cell element |
-
1989
- 1989-12-20 JP JP1332226A patent/JPH03191549A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184109B1 (en) | 1997-07-23 | 2001-02-06 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
| US6294439B1 (en) | 1997-07-23 | 2001-09-25 | Kabushiki Kaisha Toshiba | Method of dividing a wafer and method of manufacturing a semiconductor device |
| US6337258B1 (en) | 1999-07-22 | 2002-01-08 | Kabushiki Kaisha Toshiba | Method of dividing a wafer |
| JP2004327708A (en) * | 2003-04-24 | 2004-11-18 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2005166913A (en) * | 2003-12-02 | 2005-06-23 | Sharp Corp | Manufacturing method of compound semiconductor solar cell element |
| JP4562381B2 (en) * | 2003-12-02 | 2010-10-13 | シャープ株式会社 | Method for producing compound semiconductor solar cell element |
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