JPS62171112A - Manufacture of semiconductor substrate material - Google Patents
Manufacture of semiconductor substrate materialInfo
- Publication number
- JPS62171112A JPS62171112A JP1097886A JP1097886A JPS62171112A JP S62171112 A JPS62171112 A JP S62171112A JP 1097886 A JP1097886 A JP 1097886A JP 1097886 A JP1097886 A JP 1097886A JP S62171112 A JPS62171112 A JP S62171112A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- epitaxial
- growth
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000463 material Substances 0.000 title abstract description 3
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 2
- 125000005842 heteroatom Chemical group 0.000 abstract 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、異なる複数の半導体層で構成される半導体
基体の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor substrate composed of a plurality of different semiconductor layers.
(従来の技術)
従来、この種のエピタキシャル成長用半導体基板は、シ
リコン(以下Siという)基板やガリウム砒素(以下G
aAsという)基板等が用いられ、Si基板にはSt
、、 GaAs基板にはGaAsという組合せで、同種
または極めて近い種類、例えばGaAs基板にGaAt
Asという組合せで、エピタキシャル成長が行われてい
た。また、最近の有機金属化学気相成長(以下MOCV
Dという)法または分子線エピタキシャル成長(以下M
BEという)法を使うことによっテ、Si基板やrルマ
ニウム基板の上にGaAsという全く熱的性質も結晶格
子定数も異なる異質な材料の組合せによるいわゆるヘテ
ロエピタキシー成長が文献、ELECTRONIC8L
ETTER8(1984−10−25)Vol。(Prior Art) Conventionally, this type of semiconductor substrate for epitaxial growth has been made of a silicon (hereinafter referred to as Si) substrate or a gallium arsenide (hereinafter referred to as G) substrate.
aAs) substrate etc. are used, and the Si substrate is St
,, GaAs substrate is a combination of GaAs, the same type or very similar type, for example, GaAs substrate and GaAt
Epitaxial growth was performed using a combination of As. In addition, recent metal organic chemical vapor deposition (MOCV)
D) method or molecular beam epitaxial growth (hereinafter referred to as M
By using the BE method, so-called heteroepitaxy growth using a combination of different materials such as GaAs, which have completely different thermal properties and crystal lattice constants, on a Si substrate or a rumanium substrate has been reported in the literature, ELECTRONIC8L.
ETTER8 (1984-10-25) Vol.
20、 A 22. pp916−918 、やJap
anese Journal ofApplied P
hysics Vol、 23. A 11. (19
84−11)pp。20, A 22. pp916-918, YaJap
anese Journal of Applied P
hysics Vol, 23. A 11. (19
84-11)pp.
L843−L845等に記載されている方法により可能
となってきた。This has been made possible by the methods described in L843-L845 and the like.
(発明が解決しようとする問題点)
しかしながら、以上述べたような従来の方法では、例え
ば2インチのSi基板にGaAs層を3μm〜4μm厚
さにMOCVD (有機金属化学気相成長)法またはM
BE(分子線エピタキシャル成長)法により積層すると
、GaAs面を内側に基板が50μm〜60μm反シ、
さらに厚く成長させると亀裂が生じ、LSIや高周波デ
バイスなど微細なパターンを形成するときに問題となる
。(Problems to be Solved by the Invention) However, in the conventional methods as described above, for example, a GaAs layer is formed on a 2-inch Si substrate to a thickness of 3 μm to 4 μm using MOCVD (metal-organic chemical vapor deposition) or M
When laminated by BE (molecular beam epitaxial growth) method, the substrate is 50 μm to 60 μm thick with the GaAs surface inside.
When grown even thicker, cracks occur, which becomes a problem when forming fine patterns such as LSIs and high-frequency devices.
この発明の目的は以上述べたエピタキシャル成長により
積層するGaAa等の層の厚さの限界をなくし、Si基
板上へのGaAsの成長のような異質の物質をエピタキ
シャル成長するヘテロエピタキシャル成長における熱的
性質の違いによる厚さの制限をなくすことにある。また
4インチ、5インチの大型Si基板にもヘテロエピタキ
シャル成長を可能とすることを目的とする。The purpose of this invention is to eliminate the limit on the thickness of layers such as GaAa that are stacked by epitaxial growth as described above, and to eliminate the limitations on the thickness of layers such as GaAa that are stacked by the epitaxial growth described above. The goal is to eliminate thickness restrictions. Another purpose is to enable heteroepitaxial growth on large Si substrates of 4 inches and 5 inches.
(問題点を解決するだめの手段)
この発明は前記問題点を解決するために、半導体基板の
裏面に互いに直交する複数の溝を、例えばこの半導体基
板の有するオリエンテーションフラット面に平行あるい
は垂直に形成し、この半導体基板の表面にこの半導体基
板とは異なる半導体単結晶層を積層することにより半導
体基体を製造するものである。(Means for Solving the Problem) In order to solve the above problem, the present invention forms a plurality of grooves perpendicular to each other on the back surface of a semiconductor substrate, for example, parallel or perpendicular to the orientation flat surface of the semiconductor substrate. However, a semiconductor body is manufactured by laminating a semiconductor single crystal layer different from this semiconductor substrate on the surface of this semiconductor substrate.
(作用)
以上説明したように本発明によれば、半導体基板の裏面
に互いに直交する複数の溝を形成しているので、この半
導体基板の表面にこの半導体基板とは異なる半導体の単
結晶層を積層しても熱応力が緩和され基板に亀裂が生じ
ることはなく、また、LSI等の半導体装置の製造時に
機械的な力で平坦に変形させても割れることはない。(Function) As explained above, according to the present invention, a plurality of mutually orthogonal grooves are formed on the back surface of the semiconductor substrate, so that a single crystal layer of a semiconductor different from that of the semiconductor substrate is formed on the surface of the semiconductor substrate. Even when laminated, thermal stress is relaxed and no cracks occur in the substrate, and even if the substrate is deformed flat by mechanical force during the manufacture of semiconductor devices such as LSIs, no cracks will occur.
(実施例)
第1図は本発明の実施例を示すエピタキシャル用基板1
の裏面を示す図であり、第2図はその断面拡大図である
。以下、図面に沿って説明する。(Example) Fig. 1 shows an epitaxial substrate 1 showing an example of the present invention.
FIG. 2 is an enlarged cross-sectional view of the back side of FIG. The explanation will be given below along with the drawings.
まず第1図に示すように、エピタキシャル用基板1の裏
面に細い溝2(第2図参照)をオリエンテーションフラ
ット面3に平行、垂直に加工する。First, as shown in FIG. 1, a narrow groove 2 (see FIG. 2) is formed on the back surface of an epitaxial substrate 1 parallel to and perpendicular to the orientation flat surface 3. As shown in FIG.
例えば2インチ5t(100)基板をエピタキシャル用
基板1として用いる時には通常基板の厚みは200μm
〜250μmであり、細い溝加工は、100〜150μ
m深さにエツチングまたはグイシングツ−によシ行う。For example, when a 2-inch 5t (100) substrate is used as the epitaxial substrate 1, the thickness of the substrate is usually 200 μm.
~250μm, and narrow groove processing is 100~150μm
Perform etching or grouting to a depth of m.
3インチや4インチの大口径の基板については残りの厚
みが100μm〜150μmで溝加工を行う。縦横の溝
は左右上下対称が好ましく第1図に示したように3rr
、nm10.ピッチの配置を行う。溝の幅は狭くて十分
で、例えばグイシングツ−で溝加工する場合には20μ
m程度の幅の刃を使って加工する。For large-diameter substrates of 3 inches or 4 inches, grooves are formed so that the remaining thickness is 100 μm to 150 μm. It is preferable that the vertical and horizontal grooves be symmetrical in the horizontal and vertical directions, as shown in Figure 1.
, nm10. Arrange the pitch. The width of the groove is narrow and sufficient, for example 20μ when cutting grooves with a guising tool.
Process using a blade with a width of about m.
次に第2図に示すように、エピタキシャル用基板1の細
い溝2の加工をしてない面に直接あるいはバッファ層を
介して、MOCVD法あるいはMBE法により異質な単
結晶層4を成長させることによシ半導体基体を製造する
。Next, as shown in FIG. 2, a heterogeneous single crystal layer 4 is grown by MOCVD or MBE directly or via a buffer layer on the surface of the epitaxial substrate 1 where the thin grooves 2 have not been processed. A semiconductor substrate is manufactured according to the method.
例えばエピタキシャル用基板1として前記Si基板を用
いる時には、約900℃でSi基板1を熱処理すること
によシ表面を清浄にし、次にMOCVD法ならば400
〜450℃、MBE法ならば150〜400℃の低い温
度で厚さ20 nm <らいのGaAsを堆積させ、成
長をいったん中断してから基板温度を700〜750℃
に上げ2回目の成長を行うことによりGaAs単結晶層
を成長させる。For example, when using the Si substrate as the epitaxial substrate 1, the surface is cleaned by heat-treating the Si substrate 1 at about 900°C, and then, if MOCVD is used,
~450°C, or in the case of the MBE method, a 20 nm thick GaAs layer is deposited at a low temperature of 150 to 400°C, and after the growth is interrupted, the substrate temperature is increased to 700 to 750°C.
By increasing the temperature and performing a second growth, a GaAs single crystal layer is grown.
以上のようにSi基板の上にMOCVD法やMBE法に
↓り GaAs単結晶層を3〜4μm成長すると50μ
m程凹形に変形し、さらに、本発明の実施例では工ぎタ
キシャル用基板1に細い溝2を形成しているため厚くヘ
テロエピタキシャル成長を行えば行うほど凹形の変形の
度合は膜厚に比例して大きくなる。しかし、本発明の実
施例によればエピタキシャル用基板1が部分的に薄くな
っているため、応力が緩和され、厚くエピタキシャル成
長を行っても亀裂が生じることはない。As described above, when a GaAs single crystal layer is grown 3 to 4 μm thick on a Si substrate using MOCVD or MBE, the layer becomes 50 μm thick.
Further, in the embodiment of the present invention, since the narrow groove 2 is formed in the processed taxial substrate 1, the degree of the concave deformation increases as the thickness of the heteroepitaxial growth increases. becomes proportionally larger. However, according to the embodiment of the present invention, since the epitaxial substrate 1 is partially thin, the stress is relaxed and no cracks occur even if epitaxial growth is performed thickly.
また本発明の実施例によればエピタキシャル用基板1の
裏面に細い溝2を加工しているので、デバイス製作時の
マスク合せ、例えば密着露光を行う際に機械的な力で平
坦に変形してもエピタキシャル用基板1が部分的に薄い
ために割れることはない。Furthermore, according to the embodiment of the present invention, the thin groove 2 is formed on the back surface of the epitaxial substrate 1, so that it can be deformed flat by mechanical force during mask alignment during device fabrication, for example, when performing contact exposure. Also, since the epitaxial substrate 1 is partially thin, it will not break.
マタ、細い溝2はエピタキシャル用基板1のオリエンテ
ーションフラット面3に平行、垂直に加工しているので
、デバイス製作時の熱処理等において一様にその応力を
緩和することができ、デバイスの歩留り及び信頼性を向
上することができる。Since the thin grooves 2 are machined parallel to and perpendicular to the orientation flat surface 3 of the epitaxial substrate 1, stress can be uniformly relaxed during heat treatment during device fabrication, improving device yield and reliability. can improve sexual performance.
(発明の効果)
以上詳細に説明したように本発明の実施例によれば、半
導体基板の表面にこの半導体基板とは異なる半導体の単
結晶層を積層しても、この半導体基板の裏面に互いに直
交する複数の溝を形成しているので、熱応力を緩和する
ことができ、厚い前記単結晶層を有し且つ大口径の半導
体基体を製造することができる。(Effects of the Invention) As described above in detail, according to the embodiments of the present invention, even if single crystal layers of a semiconductor different from the semiconductor substrate are stacked on the front surface of the semiconductor substrate, they are mutually stacked on the back surface of the semiconductor substrate. Since a plurality of orthogonal grooves are formed, thermal stress can be alleviated, and a semiconductor substrate having a thick single crystal layer and a large diameter can be manufactured.
第1図は本発明の詳細な説明するための半導体基体の裏
面を示す平面図であシ、第2図はその半導体基体の断面
拡大図である。
1・・・エピタキシャル用基板、2・・・溝、3・・・
オリエンテーションフラット面、4・・・単結晶層。
特許出願人 沖電気工業株式会社
牟導体晃体、、N面とホキ千面図(文箱イ門)第1図
% + rJJ t=、T、Lh44本、JT−面↑
広フ(p1第2図FIG. 1 is a plan view showing the back surface of a semiconductor substrate for explaining the present invention in detail, and FIG. 2 is an enlarged cross-sectional view of the semiconductor substrate. 1... Epitaxial substrate, 2... Groove, 3...
Orientation flat surface, 4... single crystal layer. Patent applicant Oki Electric Industry Co., Ltd. Mu conductor body, N side and Hoki thousand-sided map (Text box Imon) Figure 1 % + rJJ t=, T, Lh 44 lines, JT- side ↑
Hirofu (p1 fig. 2
Claims (1)
する工程と、 該半導体基板の表面に該半導体基板とは異なる半導体単
結晶層を積層する工程とを備えてなることを特徴とする
半導体基体の製造方法。 2、前記互いに直交する溝は前記半導体基板のオリエン
テーションフラット面に平行および垂直に形成すること
を特徴とする特許請求の範囲第1項記載の半導体基体の
製造方法。[Claims] 1. A method comprising the steps of: forming a plurality of mutually orthogonal grooves on the back surface of a semiconductor substrate; and laminating a semiconductor single crystal layer different from the semiconductor substrate on the front surface of the semiconductor substrate. A method for manufacturing a semiconductor substrate, characterized in that: 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the mutually orthogonal grooves are formed parallel and perpendicular to the orientation flat surface of the semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1097886A JPS62171112A (en) | 1986-01-23 | 1986-01-23 | Manufacture of semiconductor substrate material |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1097886A JPS62171112A (en) | 1986-01-23 | 1986-01-23 | Manufacture of semiconductor substrate material |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62171112A true JPS62171112A (en) | 1987-07-28 |
Family
ID=11765248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1097886A Pending JPS62171112A (en) | 1986-01-23 | 1986-01-23 | Manufacture of semiconductor substrate material |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62171112A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001291683A (en) * | 2000-04-04 | 2001-10-19 | Disco Abrasive Syst Ltd | Method for manufacturing semiconductor chip |
JP2002134441A (en) * | 2000-10-30 | 2002-05-10 | Fuji Electric Co Ltd | Method of manufacturing power semiconductor element |
JP2007503726A (en) * | 2003-05-30 | 2007-02-22 | エス オー イ テク シリコン オン インシュレータ テクノロジース | Substrate for stressed system and crystal growth method on the substrate |
CN100461466C (en) * | 2006-02-21 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Method for avoiding aggradation thick film delamination and its manufactured solar battery |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5815225A (en) * | 1981-07-21 | 1983-01-28 | Seiko Epson Corp | Semiconductor device substrate |
JPS6066813A (en) * | 1983-09-24 | 1985-04-17 | Sharp Corp | Compound semiconductor device |
-
1986
- 1986-01-23 JP JP1097886A patent/JPS62171112A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5815225A (en) * | 1981-07-21 | 1983-01-28 | Seiko Epson Corp | Semiconductor device substrate |
JPS6066813A (en) * | 1983-09-24 | 1985-04-17 | Sharp Corp | Compound semiconductor device |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001291683A (en) * | 2000-04-04 | 2001-10-19 | Disco Abrasive Syst Ltd | Method for manufacturing semiconductor chip |
JP4687838B2 (en) * | 2000-04-04 | 2011-05-25 | 株式会社ディスコ | Manufacturing method of semiconductor chip |
JP2002134441A (en) * | 2000-10-30 | 2002-05-10 | Fuji Electric Co Ltd | Method of manufacturing power semiconductor element |
JP4617559B2 (en) * | 2000-10-30 | 2011-01-26 | 富士電機システムズ株式会社 | Method for manufacturing power semiconductor device |
JP2007503726A (en) * | 2003-05-30 | 2007-02-22 | エス オー イ テク シリコン オン インシュレータ テクノロジース | Substrate for stressed system and crystal growth method on the substrate |
JP4714688B2 (en) * | 2003-05-30 | 2011-06-29 | エス オー イ テク シリコン オン インシュレータ テクノロジース | Substrate for stressed system and crystal growth method on the substrate |
CN100461466C (en) * | 2006-02-21 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Method for avoiding aggradation thick film delamination and its manufactured solar battery |
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