JP2002134441A - Method of manufacturing power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stresses applied on a wafer in a backside manufacturing process of power semiconductor elements. SOLUTION: The manufacturing method comprises the steps of (1) sticking a surface protective tape 20 for protecting a processed surface of the wafer 10, after processing the surface of the wafer 10 for power semiconductor substrate elements, (2) grinding the backside, (3) dicing (first) the backside of the wafer 10 along dicing lines, (4) implanting ions into the backside, (5) heat- treating it, (6) depositing a metal film on the backside, (7) removing the tape thereafter, (8) dicing (second) along the dicing lines, thereby manufacturing chips.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device comprising a thin substrate having a processing step on a back surface.

[0002]

2. Description of the Related Art When power conversion and power control are conventionally performed, a power semiconductor device, which is a power semiconductor element, is indispensable as a key device, and its application fields are power, transportation, industry, information, communication, and the like. There are a wide variety of household appliances. In particular, IGBT (Insulated Gate Bipolar Transis
tor) is being put to practical use in applications such as low-loss, low-noise inverters and the like, which are not good at power MOS FETs and require high-voltage, high-current, high-speed operation.

In recent years, in the field of semiconductors, there is an increasing demand for low on-voltage and low cost, and there is also a strong demand for miniaturization and thinning. Therefore, for example, in the IGBT, chip formation has been performed using an FZ substrate instead of using an epitaxial substrate, which has conventionally been a factor of high cost. In the chip formation, after the front surface process is completed, a back surface manufacturing process of performing back wrap, ion implantation, back surface heat treatment, electrode formation by metal deposition, and the like is performed.
Hereinafter, an example of a non-punch-through IGBT will be described. FIG. 5 shows a conventional back surface manufacturing process of a non-punch-through IGBT.

In the manufacturing process of a wafer (hereinafter sometimes referred to as a substrate), (1) a fine structure forming process such as film formation, photolithography, ion implantation for impurity diffusion introduction, diffusion, etc. is used in the surface process. The front side is manufactured. In a basic backside manufacturing process, (2) resist coating is first performed to protect the front side.
In the subsequent (3) back wrap, the back surface of the wafer is shaved by the background (BG) to make the wafer thin. Next, (4) backside ion implantation is performed, and (5) ashing of the resist applied to the front side, (6) heat treatment of the backside, and (7) backside metal film deposition as an electrode layer are performed.

FIG. 6 shows a change in the amount of warpage in a conventional back surface manufacturing process. 6 correspond to the numerical values (1) to (7) of the back surface manufacturing process shown in FIG. Also,
The amount of warpage on the vertical axis indicates the stress direction and its magnitude as viewed from the substrate surface. When the amount of warpage is 0, the horizontal state is maintained between the center and the end of the wafer, and the wafer is not warped on either the front side or the back side. In the state where the amount of warpage is plus (+), stress acts in the pulling direction as viewed from the surface, and the end is warped toward the surface toward the center of the wafer. On the other hand, a state in which the amount of warpage is minus (-) is a state in which an end is warped toward the back surface side with respect to the center of the wafer because stress acts in the compression direction as viewed from the front surface.

Step (1) The amount of warpage when the surface processing is completed is set to zero. In the step (2) resist coating, the amount of warp hardly changes, but after the step (3) background processing, a tensile stress acts, and the end of the wafer warps by about 2 mm toward the surface side. After the resist is peeled off by the following step (5) ashing of the resist, a slight compressive stress acts, and a tensile stress acts by the step (6) heat treatment on the back surface. Then, in step (7), a very large compressive stress (tensile stress as viewed from the back side) acts on the front side due to backside deposition, and the amount of warpage is −3.1 mm (the center and the edge of the warped wafer). Difference).

In the embodiment shown in FIG. 6, the resist film thickness for protecting the surface is 3 μm, and the pack ground is 350 μm.
This is a sample obtained by shaving the FZ-N substrate from 150 μm to 150 μm.
The back metal film was formed by evaporating 3 μm of Ni. Thereafter, a desired chip size was obtained by a wafer check and dicing operation.

[0008]

However, in the conventional backside manufacturing process, since the wafer is thin, many process problems arise due to warpage caused by stress.

For example, after a metal film is deposited, the metal film becomes a film having a large compression pressure when viewed from the substrate side, and the wafer may be broken. In addition, even if it does not break, there is a problem that it becomes difficult to perform the dicing step due to the warpage generated by the compression pressure. Further, the shape of the chip after dicing may be distorted, and the IGBT characteristics as theoretical may not be obtained. As a result, it has been difficult to improve the productivity in the manufacturing process of the power semiconductor element requiring the back surface manufacturing process.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a power semiconductor device capable of reducing stress applied to a wafer in a process of manufacturing a back surface of the power semiconductor device. With the goal.

[0011]

According to the present invention, there is provided a method for manufacturing a power semiconductor device comprising a thin substrate having a processing step on a back surface, the method comprising the steps of: Prior to deposition of a backside metal film for an electrode on the backside of the substrate, a tape for surface protection is attached to the surface of the substrate, and a first dicing is performed to cut the substrate along a dicing line from the backside of the substrate,
A step of removing the tape for protecting the substrate surface after performing the backside metal film deposition, and performing a second dicing for cutting the substrate along the dicing line. , Are provided.

In the method for manufacturing a power semiconductor device in such a process, after the substrate surface of the power semiconductor substrate device is processed, before the step of depositing a back surface metal film for an electrode on the back surface of the substrate, A tape for protecting the surface that protects the processing performed on the surface of the substrate is attached, and first dicing is performed to cut the substrate along the dicing line from the back surface of the substrate. After that, a backside metal film deposition step is performed. After performing the backside metal film deposition, the tape for protecting the substrate surface is removed, and a second dicing for cutting the substrate along the dicing line is performed to manufacture a chip.

According to another aspect of the present invention, there is provided a method of manufacturing a power semiconductor device comprising a thin substrate having a processing step on a back surface. Prior to deposition of the backside metal film, a tape for surface protection is attached to the surface of the substrate, a tensile stress film is formed on the tape for surface protection, and then a cut is formed in the substrate along the dicing line from the backside of the substrate. Or a first dicing for making a cut in the substrate along a dicing line from the back side of the substrate, and then forming a tensile stress film on the tape for surface protection. After performing the backside metal film deposition, the tape for protecting the substrate surface and the tensile stress film are removed, and the substrate is cut along the dicing line. The method of manufacturing a power semiconductor device and having a second step of performing dicing for cutting, are provided.

In the method of manufacturing a power semiconductor device in such a process, after the substrate surface of the power semiconductor substrate device is processed, before the step of depositing a back surface metal film for an electrode on the back surface of the substrate, A tape for protecting the surface that protects the processing performed on the substrate surface is attached. Subsequently, a first dicing is performed in which a tensile stress film is formed on the surface protecting tape and a cut is made in the substrate along a dicing line from the back surface side of the substrate. Either of the formation of the tensile stress film and the first dicing may be performed first. After that, a backside metal film deposition step is performed. After performing the backside metal film deposition, the tape for protecting the substrate surface and the tensile stress film formed on the tape for protecting the surface of the substrate are removed, and the second dicing for cutting the substrate along the dicing line is performed to manufacture a chip. .

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a procedure of a back surface manufacturing process by a method for manufacturing a power semiconductor device according to a first embodiment of the present invention.

In the method of manufacturing a power semiconductor device according to the first embodiment of the present invention, after the front surface forming process is completed, as a back surface manufacturing step, (1) tape bonding, (2) background , (3) dicing (first time), (4) backside ion implantation, (5) heat treatment, (6) backside metal film deposition, (7) tape removal, (8) dicing (second time) Are sequentially performed.

(1) In the tape attaching step, a tape (hereinafter, referred to as a tape) 20 for protecting the substrate surface is attached to the surface of the wafer 10 on which the surface forming process has been completed.
The tape 20 is made of (5) a heat-resistant material that can withstand heat treatment;
For example, it is a heat-resistant polyimide tape. The heat-resistant polyimide tape can withstand heat up to about 400 ° C. Also, by applying the tape 20 to the surface of the wafer 10, the step of applying a resist for protecting the surface can be omitted. Further, since no resist coating is performed, the resist ashing step can be omitted.

(2) The background (BG) step is a step of shaving the back surface of the wafer 10 to reduce the thickness of the wafer 10. (3) The dicing (first) step is a step of performing first dicing in which a cut is made along the dicing line from the back surface side of the substrate. In dicing (first time), when dicing is performed from the back side, the tape 20
Slightly (for example, about several μm) from the front side of the wafer. In the dicing process (first time), the tensile stress generated by the resist coating and the background process in the conventional process can be reduced by making a cut in the wafer 10. By doing so, the stress generated on the wafer 10 is almost eliminated, and the amount of warpage can be reduced.

Subsequently, similarly to the conventional back surface manufacturing process,
(4) Backside ion implantation, (5) Heat treatment, and (6) Backside metal film deposition. (6) In the step of depositing the back metal film, for example, Ni is deposited on the back surface of the wafer 10 to form the back metal film 30. When the back metal film 30 was formed by the conventional manufacturing method, a very large compressive stress was applied when viewed from the front side. However, in the manufacturing method according to the present invention, (3) dicing (first time)
The compressive stress can be reduced by the cut formed in the step (1). For this reason, (4) the process after the back surface ion implantation can proceed smoothly without being affected by the stress, that is, without being affected by the warpage of the wafer 10.

(7) The tape removing step includes the step of removing the back metal film 3
The tape 20 attached to the surface of the wafer 10 on which the 0 is formed is removed. (8) The dicing (second time) process is as follows: (7) After removing the tape, (3) dicing (first time) several μm
The dicing is performed along the dicing line of the wafer 10 where m is left, and the wafer 10 is formed into chips. If the chips cannot be cut properly, dicing may be performed again.

Next, generation of stress in each step of the manufacturing method according to the first embodiment of the present invention will be described in Example 1. FIG. 2 shows a change in the amount of warpage in the back surface manufacturing process according to the first embodiment of the present invention. 2 correspond to the numerical values (1) to (8) of the back surface manufacturing process shown in FIG. Further, the amount of warping on the vertical axis indicates the stress direction and the magnitude thereof as viewed from the substrate surface. A state where the amount of warpage is plus (+) is a state where stress acts in the tensile direction as viewed from the surface, and a state where the amount of warpage is minus (−) is a state where stress is acting in the direction of compression as viewed from the surface.

Step (1) The amount of warpage when the tape application is completed is almost zero. Step (2) After the completion of the background, a slight tensile stress acts, and the edge of the wafer is warped by about 1.5 mm toward the surface side. This value is
The amount of warpage caused by the conventional background (about 2 m
m). By performing dicing on the substrate in the next step (3) dicing (first time), the stress applied to the substrate is almost eliminated, and the amount of warpage returns to almost zero. There is almost no change in the amount of warpage due to the process (4) back surface ion implantation and the process (5) heat treatment. Then, a slight compressive stress (a tensile stress when viewed from the back side) acts on the front side due to the rear surface metal film deposition in the step (6). The amount of warpage is-
0.8 mm, compared to -3.1 mm of the conventional example.
The amount of warpage can be reduced by as much as 3 mm. Since the warpage is further reduced by removing the tape in the step (7), the cutting process in the step (8) dicing (second time) is facilitated. As a result, chip productivity is improved.

As described above, in the manufacturing method according to the first embodiment of the present invention, the tape 20 is provided on the front surface side of the wafer 10, and the dicing (first time) is performed from the back surface side of the wafer 10. The process after the implantation can proceed smoothly with almost no influence of stress. Thereby, a chip element can be manufactured with high productivity. In addition, since the steps of resist application and resist ashing can be omitted, the occurrence of cracks due to spin coating or the like can be eliminated. This also contributes to an improvement in the productivity of chip element manufacturing.

Next, a method of manufacturing a power semiconductor device according to a second embodiment of the present invention will be described. FIG.
9 is a procedure of a back surface manufacturing process according to the method for manufacturing a power semiconductor device according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

In the method for manufacturing a power semiconductor device according to the second embodiment of the present invention, after the front surface forming process is completed, as a back surface manufacturing step, (1) tape bonding, (2) background (3) dicing (first time), (4) surface deposition film formation, (5) back surface ion implantation,
Steps of (6) heat treatment, (7) vapor deposition of the back metal film, (8) removal of the tape and the surface vapor-deposited film, and (9) dicing (second time) are sequentially performed.

(1) In the tape attaching step, the tape 20 is attached to the surface of the wafer 10 on which the surface forming process has been completed. The tape 20 is, for example, a heat-resistant polyimide tape.

(2) The background (BG) step is a step of shaving the back surface of the wafer 10 to reduce the thickness of the wafer 10. (3) The dicing (first) step is a step of performing first dicing in which a cut is made along the dicing line from the back surface side of the substrate. In dicing (first time), when dicing is performed from the back side, the tape 20
Slightly (for example, about several μm) from the front side of the wafer.

(4) The step of forming the surface deposited film is performed by using the tape 2
In order to form a tensile stress film, a surface vapor-deposited film 40 such as a metal film is formed on the substrate 0. Here, for example, an Al metal film is formed by evaporation as a surface evaporation film. The surface-deposited film 40 exerts a tensile stress as viewed from the front side of the wafer 10 and (3) firmly holds chips that have become difficult to hold in the dicing (first) step. The surface deposited film 40 deposited on the tape 20 has a tensile stress, but the stress is low because the wafer 10 has already been diced. Also, here
As the tensile stress film, a metal film is vapor-deposited on the tape 20 to form the surface-deposited film 40. However, even if polyimide is applied on the tape 20 by a spin coating method, a tensile stress film is similarly formed. Can be.

Subsequently, similarly to the conventional back surface manufacturing process,
(5) Backside ion implantation, (6) Heat treatment, (7) Backside metal film deposition. (7) The backside metal film is deposited on the backside of the wafer 10 by, for example, N
i is deposited to form a back metal film 30. When the back metal film 30 is formed by the conventional manufacturing method, a very large compressive stress is applied when viewed from the front surface side. However, in the manufacturing method according to the present invention, (3) dicing (first time) is performed. The notch can reduce the compressive stress. For this reason, (5) the process after the back surface ion implantation can be smoothly performed with almost no influence of stress.

(8) In the removal of the tape and the surface deposited film, the tape 20 and the surface deposited film 40 attached to the surface of the wafer 10 on which the back metal film 30 is formed are removed. (9) Dicing (second time) is (8) After the removal of the tape and the surface deposited film is completed, (3) Dicing (first time)
Then, dicing is performed along the dicing line of the wafer 10 left by several μm to make the wafer 10 into a chip.
If the chips cannot be cut properly, dicing may be performed again.

In the above description, the surface deposition film 40 is formed after dicing (first time). However, the surface deposition film 40 can be formed before dicing (first time) or before background. The deposition of the front surface deposition film 40 may be performed at any stage after the tape is attached and before the back surface metal deposition is performed.

Next, generation of stress in each step of the manufacturing method according to the second embodiment of the present invention will be described in Example 2. In Example 2, an Al metal film having a thickness of 3 μm was deposited as a film to be deposited on the tape 20. FIG. 4 shows a change in the amount of warpage in the back surface manufacturing process according to the second embodiment of the present invention. As in FIG. 2, the processes on the horizontal axis correspond to (1) to (9) of the back surface manufacturing process shown in FIG. 3, and the amount of warpage on the vertical axis indicates the stress direction and its magnitude as viewed from the substrate surface. ing.

Step (1) The amount of warpage when the tape application is completed is almost zero. Step (2) After the completion of the background, a slight tensile stress acts, and the edge of the wafer is warped by about 1.5 mm toward the surface side. This value is the amount of warpage caused by the conventional background (about 2 mm)
Less than compared to. By performing dicing on the substrate in the next step (3) dicing (first time), the stress applied to the substrate is almost eliminated, and the amount of warpage returns to almost zero. Step (4) The surface deposited film 40 formed on the tape 20 by the film deposition of the surface deposited film has a tensile stress, but the value is 0.3 m since the wafer is already diced.
m. Step (5) Backside ion implantation, Step (6)
By heat treatment, the amount of warp increases to 0.5 mm,
(7) When a backside metal film is deposited, a very small compressive stress (tensile stress when viewed from the backside) acts when viewed from the front side. The amount of warpage is -0.1 mm, and there is hardly any warpage due to stress. Conventional Example -3.1
The warpage due to the stress can be reduced by 3 mm as compared with the mm. As described above, since the amount of warpage generated by the stress can be reduced, chip productivity is improved.

As described above, in the manufacturing method according to the second embodiment of the present invention, the tape 20 is provided on the front surface side of the wafer 10, dicing (first time) is performed from the back surface side of the wafer 10, By forming the top surface deposited film 40 on the upper surface, the process after back surface ion implantation can be smoothly performed with almost no influence of stress. Thereby, a chip element can be manufactured with high productivity. Further, by forming the surface deposited film 40, which is a tensile stress film, on the tape 20, the chip can be held firmly, and the labor required for the operation can be further reduced. In addition to these, similarly to the first embodiment, the steps of resist coating and resist ashing can be omitted, so that the occurrence of cracks due to spin coating or the like can be eliminated. This also contributes to an improvement in the productivity of chip element manufacturing.

[0035]

As described above, according to the present invention, a tape for protecting the surface of the substrate is attached after the surface of the substrate is processed and before the step of depositing the back surface metal film for the electrode on the back surface of the substrate. Then, dicing is performed along the dicing line from the back side of the substrate. After performing the backside metal film deposition, the tape for protecting the substrate surface is removed, and dicing is performed again along the dicing line to manufacture a chip.

As described above, by applying the tape for protecting the front surface and performing dicing along the dicing line from the back surface of the substrate, the stress applied to the wafer in the process of manufacturing the back surface of the power semiconductor element can be reduced. . As a result, a power semiconductor element requiring a back surface manufacturing step can be manufactured with high productivity.

In the present invention, after processing the substrate surface, a tape for protecting the surface is applied before the step of depositing the back surface metal film for the electrode on the back surface of the substrate. Subsequently, a tensile stress film is formed on the tape for protecting the surface, and dicing is performed along the dicing line from the back surface of the substrate. Either the formation of the tensile stress film or the dicing may be performed first. After the backside metal film is deposited, the tape for protecting the surface of the substrate and the tensile stress film are removed, and dicing is performed again along the dicing line to manufacture a chip.

As described above, the surface protection tape is attached, the tensile stress film is formed on the tape, and the dicing is performed along the dicing line from the back surface of the substrate. In this case, the stress applied to the wafer can be further reduced. As a result, a power semiconductor element requiring a back surface manufacturing step can be manufactured with high productivity.

[Brief description of the drawings]

FIG. 1 shows a procedure of a back surface manufacturing step by a method of manufacturing a power semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a change in the amount of warpage in the back surface manufacturing process according to the first embodiment of the present invention.

FIG. 3 shows a procedure of a back surface manufacturing step by a method for manufacturing a power semiconductor device according to a second embodiment of the present invention.

FIG. 4 shows a change in the amount of warpage due to a back surface manufacturing process according to a second embodiment of the present invention.

FIG. 5 shows a conventional backside manufacturing process of a non-punch-through IGBT.

FIG. 6 shows a change in the amount of warpage due to a conventional back surface manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Wafer 20 Tape 30 Backside metal film 40 Surface evaporation film

Claims (6)

[Claims] 1. A method of manufacturing a power semiconductor device comprising a thin substrate having a processing step on a back surface, wherein after processing the surface of the substrate, the substrate is subjected to deposition of a back surface metal film for an electrode on the back surface of the substrate. A tape for surface protection is attached to the front surface, a first dicing is performed to cut the substrate along a dicing line from the back surface side of the substrate, and after performing the back surface metal film deposition, the tape for substrate surface protection is applied. Removing the substrate along the dicing line and performing a second dicing process for the power semiconductor device. 2. The method according to claim 1, wherein the surface protection tape is a heat-resistant polyimide tape. 3. A method for manufacturing a power semiconductor device comprising a thin substrate having a processing step on a back surface, wherein after processing the surface of the substrate, the substrate is processed prior to deposition of a back surface metal film for an electrode on the back surface of the substrate. A tape for protecting the surface is attached to the front surface, a tensile stress film is formed on the tape for protecting the surface, and then a first dicing is performed to cut the substrate along a dicing line from the back side of the substrate. Or a first dicing process in which the substrate is cut along the dicing line from the back side of the substrate, and then a tensile stress film is formed on the tape for protecting the front surface; After that, the tape for protecting the substrate surface and the tensile stress film are removed, and a second dicing for cutting the substrate along the dicing line is performed. A method for manufacturing a power semiconductor device, comprising the steps of: 4. The method according to claim 3, wherein the surface protection tape is a heat-resistant polyimide tape. 5. The method according to claim 3, wherein the tensile stress film is a metal film. 6. The method according to claim 3, wherein the tensile stress film is a polyimide film.