JPH04335551A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04335551A
JPH04335551A JP10716791A JP10716791A JPH04335551A JP H04335551 A JPH04335551 A JP H04335551A JP 10716791 A JP10716791 A JP 10716791A JP 10716791 A JP10716791 A JP 10716791A JP H04335551 A JPH04335551 A JP H04335551A
Authority
JP
Japan
Prior art keywords
groove
dicing
conductive film
back surface
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10716791A
Other languages
Japanese (ja)
Inventor
Takeshi Sekiguchi
剛 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP10716791A priority Critical patent/JPH04335551A/en
Publication of JPH04335551A publication Critical patent/JPH04335551A/en
Pending legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device, in which a dicing step of a semiconductor wafer having a conductive film formed on its rear surface is smoothly performed and to provide a mounting structure of an optical module having excellent noise resistance. CONSTITUTION:A step of forming a groove on a rear surface of a semiconductor wafer 5 along a scribing line, a step of covering the rear surface having the formed groove and forming a conductive film 1 in the groove G, and a step of cutting the film 1 formed in the groove G by dicing the wafer 5 having the formed film 1 along the scribing line from the front surface, are provided.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は裏面に導電膜が形成され
た半導体ウエハのダイシングにより製造される半導体装
置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device by dicing a semiconductor wafer having a conductive film formed on its back surface.

【0002】0002

【従来の技術】半導体材料は一般に脆性材料なので、チ
ップのエッジが欠け易く、その為、ダイシングブレード
も脆性材料の切断に最適な材料、構造が採用されている
(“ダイシング”、pp.42−51、半導体実装技術
ハンドブック(サイエンスフォーラム)参照)。
[Prior Art] Semiconductor materials are generally brittle materials, so the edges of chips are easily chipped. Therefore, dicing blades are also made of materials and structures that are optimal for cutting brittle materials ("Dicing", pp. 42- 51, Semiconductor Packaging Technology Handbook (Science Forum)).

【0003】ところで、裏面に金属膜が形成された半導
体装置を作製する場合、一般的に半導体ウエハの裏面に
金属膜を形成しておき、この半導体ウエハを表面側のス
クライブラインに沿って裏面金属膜と共にダイシングす
る。裏面に金属膜が形成された半導体装置としては、マ
イクロ波デバイス、パワーデバイスが知られており、マ
イクロ波デバイスは裏面側に比較的厚い金属膜を形成す
ることによりマイクロ波における表皮効果の導体抵抗を
低減しており(“マイクロ波と金属板”、pp.14−
21、マイクロ波、阿部著、東京大学出版会)、パワー
デバイスは厚みの小さいウエハに裏面に厚い金属膜を形
成することにより熱抵抗を低減している(“FETの熱
抵抗”、pp.77−81、化合物半導体デバイスハン
ドブック(サイエンスフォーラム)参照)。
By the way, when manufacturing a semiconductor device with a metal film formed on the back surface, the metal film is generally formed on the back surface of the semiconductor wafer, and the back surface metal film is formed along the scribe line on the front side of the semiconductor wafer. Dice together with the membrane. Microwave devices and power devices are known as semiconductor devices with a metal film formed on the back side. Microwave devices reduce the conductor resistance of the skin effect in microwaves by forming a relatively thick metal film on the back side. (“Microwaves and Metal Plates”, pp.14-
21, Microwave, Abe, University of Tokyo Press), power devices reduce thermal resistance by forming a thick metal film on the back side of a thin wafer (“Thermal Resistance of FETs”, pp. 77) -81, Compound Semiconductor Device Handbook (Science Forum)).

【0004】図4は裏面に金属膜1が形成された半導体
ウエハ2をテープ3上に固定し、上述したダイシングブ
レード4で切断する状態を示す断面図である。
FIG. 4 is a cross-sectional view showing a state in which a semiconductor wafer 2 having a metal film 1 formed on its back surface is fixed on a tape 3 and cut with the above-mentioned dicing blade 4.

【0005】[0005]

【発明が解決しようとする課題】図示したように、裏面
に形成された金属膜1は一般的に延性を有するので、ダ
イシングの際に金属膜1が切断されずにダイシングブレ
ード4から逃げ、半導体ウエハ2が分割されないという
問題があった。
[Problems to be Solved by the Invention] As shown in the figure, since the metal film 1 formed on the back surface is generally ductile, the metal film 1 escapes from the dicing blade 4 without being cut during dicing, and the semiconductor There was a problem that the wafer 2 was not divided.

【0006】そこで本発明は、裏面に金属等の導電膜が
形成された半導体ウエハのダイシング工程に支障を与え
ない半導体装置の製造方法を提供することを目的とする
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that does not interfere with the dicing process of a semiconductor wafer having a conductive film of metal or the like formed on the back surface.

【0007】[0007]

【課題を解決するための手段】上記課題を達成するため
に、本発明はスクライブラインに沿って半導体ウエハの
裏面に溝を形設する工程と、溝が形設された裏面に導電
材を被着し溝内に導電膜を形成する工程と、導電膜が形
成された半導体ウエハを表面からスクライブラインに沿
ってダイシングすることにより溝内に形成された導電膜
を切断する工程とを含む。
[Means for Solving the Problems] In order to achieve the above object, the present invention includes a process of forming grooves on the back surface of a semiconductor wafer along scribe lines, and covering the back surface on which the grooves are formed with a conductive material. The method includes a step of forming a conductive film in the groove, and a step of cutting the conductive film formed in the groove by dicing the semiconductor wafer on which the conductive film is formed along the scribe lines from the front surface.

【0008】[0008]

【作用】本発明に係る半導体装置の製造方法によると、
ダイシング工程前に半導体ウエハの裏面にはスクライブ
ラインに沿って溝が形設され、導電膜の切断は当該溝内
で行われる。この場合、溝の深さがダイシングブレード
の切り込み可能な量として寄与するので、ダイシング工
程において導電膜の逃げ量を越えた切り込みが可能にな
る。
[Operation] According to the method of manufacturing a semiconductor device according to the present invention,
Before the dicing process, a groove is formed on the back surface of the semiconductor wafer along the scribe line, and the conductive film is cut within the groove. In this case, since the depth of the groove contributes to the amount of cut that can be made by the dicing blade, it becomes possible to make a cut that exceeds the amount of relief of the conductive film in the dicing process.

【0009】[0009]

【実施例】以下、本発明の一実施例について、添付図面
を参照して説明する。なお、説明において同一要素には
同一符号を用い、重複する説明は省略する。図1は一実
施例に係る半導体装置としてGaAsICを製造する方
法を示す工程図、図2はその工程を示すフローチャート
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 is a process diagram showing a method for manufacturing a GaAs IC as a semiconductor device according to an embodiment, and FIG. 2 is a flowchart showing the process.

【0010】まず、GaAs基板5の表面に半導体素子
を形成する(ステップ101)。次に、このGaAs基
板5の裏面にレジスト材をスピンコーテイングで塗付し
(ステップ102)、裏面全体にレジスト膜6を形成す
る(図1(a))。次に、このレジスト膜6に露光、現
像を施すことにより(ステップ103)、スクライブラ
インに沿って開口Aを有するレジストパターンを形成す
る(図1(b))。この場合、開口Aの幅は厚さ100
〜150μmのGaAs基板5に対して、例えば10〜
50μm程度に設定することができる。このレジストパ
ターンをマスクとして用い、GaAs基板5にRIE(
Reactive IonEtching)などのドラ
イエッチングを施す(ステップ104)。その後、レジ
スト膜6をGaAs基板5の裏面から除去する。図3(
a)はレジスト膜6を除去した後のGaAs基板5の裏
面側を示す全体図、同図(b)はその一部を拡大して示
す図である。図示したように、このドライエッチングに
より、断面が略台形状の溝Gがスクライブラインに沿っ
てGaAs基板5の裏面に形設される(図1(c))。 次に、レジストパターンを除去して金属を被着し(ステ
ップ105)、GaAs基板5の裏面に金属膜(導電膜
)1を形成する(図1(d))。その後、このGaAs
基板5の裏面に膜厚50〜100μmのテープ3を粘着
し(図1(e))、ダイシングブレード4でスクライブ
ラインに沿って表面からGaAs基板5をチップ状に分
割する(図1(f)、ステップ106)。
First, a semiconductor element is formed on the surface of the GaAs substrate 5 (step 101). Next, a resist material is applied to the back surface of this GaAs substrate 5 by spin coating (step 102) to form a resist film 6 on the entire back surface (FIG. 1(a)). Next, this resist film 6 is exposed and developed (step 103) to form a resist pattern having openings A along the scribe lines (FIG. 1(b)). In this case, the width of opening A is 100 mm thick.
For example, 10 to 150 μm GaAs substrate 5
It can be set to about 50 μm. Using this resist pattern as a mask, the GaAs substrate 5 is subjected to RIE (
Dry etching such as reactive ion etching is performed (step 104). Thereafter, the resist film 6 is removed from the back surface of the GaAs substrate 5. Figure 3 (
1A is an overall view showing the back side of the GaAs substrate 5 after the resist film 6 has been removed, and FIG. 1B is an enlarged view of a portion thereof. As shown in the figure, by this dry etching, a groove G having a substantially trapezoidal cross section is formed on the back surface of the GaAs substrate 5 along the scribe line (FIG. 1(c)). Next, the resist pattern is removed and metal is deposited (step 105), and a metal film (conductive film) 1 is formed on the back surface of the GaAs substrate 5 (FIG. 1(d)). After that, this GaAs
A tape 3 with a film thickness of 50 to 100 μm is adhered to the back surface of the substrate 5 (FIG. 1(e)), and the GaAs substrate 5 is divided into chips from the surface along the scribe line with a dicing blade 4 (FIG. 1(f)). , step 106).

【0011】このように、本実施例による製造方法では
ダイシング工程の前に形設された溝Gの内部で金属膜1
が切断されるので、ダイシングブレード4は溝Gの底部
に被着した金属膜1の逃げに追従することができ、確実
に金属膜1は切断される。
As described above, in the manufacturing method according to this embodiment, the metal film 1 is formed inside the groove G formed before the dicing process.
Since the metal film 1 is cut, the dicing blade 4 can follow the escape of the metal film 1 deposited on the bottom of the groove G, and the metal film 1 is reliably cut.

【0012】なお、本発明は上記実施例に限定されるも
のではない。例えば、エッチング法はRIEに限らず、
RIE以外のドライエッチング、ウエットエッチング(
ケミカルエッチングなど)を使用することができる。
It should be noted that the present invention is not limited to the above embodiments. For example, etching methods are not limited to RIE,
Dry etching other than RIE, wet etching (
chemical etching, etc.).

【0013】通常、GaAsIC(数GHzで動作)の
裏面金属はTiを500〜1000オングストローム、
Auを1500〜3000オングストロームの膜厚でス
パッタリングあるいは蒸着することにより形成される。 しかし、特にマイクロ波デバイス、パワーデバイスの場
合には、さらに、Auを電解メッキで2〜50μmの膜
厚で被着するので裏面金属は一層厚くなり、幅が広く深
い溝が必要になる。この場合、例えばエッチングレート
の高いエッチャントを用いたウエットエッチングにより
、幅、深さの大きい溝を形成することができる。
[0013] Normally, the back metal of GaAs IC (operating at several GHz) is made of Ti with a thickness of 500 to 1000 angstroms.
It is formed by sputtering or vapor depositing Au to a thickness of 1500 to 3000 angstroms. However, especially in the case of microwave devices and power devices, since Au is further deposited with a thickness of 2 to 50 μm by electrolytic plating, the back metal becomes even thicker, and a wide and deep groove is required. In this case, a groove with a large width and depth can be formed by wet etching using an etchant with a high etching rate, for example.

【0014】また、上記実施例ではウエハ表面に半導体
素子を形成してから裏面にスクライブラインに沿った溝
を形成しているが、溝を形成した後で半導体素子を表面
に形成してもよい。
Furthermore, in the above embodiment, semiconductor elements are formed on the front surface of the wafer, and then grooves are formed on the back surface along the scribe lines, but semiconductor elements may be formed on the front surface after forming the grooves. .

【0015】[0015]

【発明の効果】本発明は、ダイシング前に形設された溝
内で導電膜が切断されるので、ダイシングブレードは導
電膜の逃げに追従することができ、ダイシング工程に支
障を来すことなく半導体装置を製造することができる。
[Effects of the Invention] In the present invention, since the conductive film is cut within the grooves formed before dicing, the dicing blade can follow the escape of the conductive film, without causing any trouble to the dicing process. Semiconductor devices can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例に係る半導体装置の製造方法
を半導体ウエハの縦断面図により示す工程図である。
FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention using longitudinal cross-sectional views of a semiconductor wafer.

【図2】本発明の一実施例に係る半導体装置の製造方法
を示すフローチャートである。
FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】半導体ウエハのレジスト膜を除去した後のGa
As基板の裏面側を示す平面図である。
[Figure 3] Ga after removing the resist film of the semiconductor wafer
FIG. 3 is a plan view showing the back side of the As substrate.

【図4】従来の半導体装置の製造方法におけるダイシン
グ状態を示す縦断面図である。
FIG. 4 is a longitudinal cross-sectional view showing a dicing state in a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1…金属膜 2…半導体ウエハ 3…テープ 4…ダイシングブレード 5…GaAs基板 6…レジスト膜 A…開口 G…溝 1...Metal film 2...Semiconductor wafer 3...Tape 4...Dicing blade 5...GaAs substrate 6...Resist film A...Aperture G...Groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  裏面に導電膜が形成された半導体ウエ
ハのダイシングにより製造される半導体装置の製造方法
において、スクライブラインに沿って半導体ウエハの裏
面に溝を形設する工程と、前記溝が形設された裏面に導
電材を被着し前記溝内に導電膜を形成する工程と、前記
導電膜が形成された半導体ウエハを表面からスクライブ
ラインに沿ってダイシングすることにより前記溝内に形
成された導電膜を切断する工程とを含む半導体装置の製
造方法。
1. A method for manufacturing a semiconductor device manufactured by dicing a semiconductor wafer having a conductive film formed on the back surface, comprising: forming a groove on the back surface of the semiconductor wafer along a scribe line; A conductive film is formed in the groove by depositing a conductive material on the back surface of the groove, and dicing the semiconductor wafer on which the conductive film is formed along the scribe line from the front surface. A method for manufacturing a semiconductor device, the method comprising: cutting a conductive film formed by cutting the conductive film.
JP10716791A 1991-05-13 1991-05-13 Manufacture of semiconductor device Pending JPH04335551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10716791A JPH04335551A (en) 1991-05-13 1991-05-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10716791A JPH04335551A (en) 1991-05-13 1991-05-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04335551A true JPH04335551A (en) 1992-11-24

Family

ID=14452186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10716791A Pending JPH04335551A (en) 1991-05-13 1991-05-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04335551A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134441A (en) * 2000-10-30 2002-05-10 Fuji Electric Co Ltd Method of manufacturing power semiconductor element
US9362366B2 (en) 2013-05-13 2016-06-07 Panasonic Intellectual Property Management Co., Ltd. Semiconductor element, semiconductor element manufacturing method, semiconductor module, semiconductor module manufacturing method, and semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134441A (en) * 2000-10-30 2002-05-10 Fuji Electric Co Ltd Method of manufacturing power semiconductor element
JP4617559B2 (en) * 2000-10-30 2011-01-26 富士電機システムズ株式会社 Method for manufacturing power semiconductor device
US9362366B2 (en) 2013-05-13 2016-06-07 Panasonic Intellectual Property Management Co., Ltd. Semiconductor element, semiconductor element manufacturing method, semiconductor module, semiconductor module manufacturing method, and semiconductor package

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