JP2002134451A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JP2002134451A
JP2002134451A JP2000328179A JP2000328179A JP2002134451A JP 2002134451 A JP2002134451 A JP 2002134451A JP 2000328179 A JP2000328179 A JP 2000328179A JP 2000328179 A JP2000328179 A JP 2000328179A JP 2002134451 A JP2002134451 A JP 2002134451A
Authority
JP
Japan
Prior art keywords
wafer
grinding
groove
warpage
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000328179A
Other languages
Japanese (ja)
Inventor
Makoto Takayama
高山  誠
Tadaaki Soma
忠昭 相馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000328179A priority Critical patent/JP2002134451A/en
Publication of JP2002134451A publication Critical patent/JP2002134451A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional constitutions, where a warpage is produced in a wafer by the thermal distortion and the difference in linear expansion coefficients of nitride films in the heat treatment process of a semiconductor element region forming process, and as the thickness of the wafer is reduced in recent times, many cracking damages of wafers caused by the warpages are produced in wafers, whose finished thicknesses are not thicker than 150 μm in a B/G grinding process. SOLUTION: Grooves are formed on dicing streets used in an assembly process by etching in a plasma treatment. Using such a constitution, a tensile stress causing a warpage is divided and the warpage is reduced before a B/G grinding process, so that the tightness between a table and a wafer can be improved; and even if the finished thickness of the wafer is thinner than the conventional thickness, defects produced by wafer crackings and damages can be significantly reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、薄膜ウエファの裏面研削時にウエファダメー
ジを防ぐ半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which prevents wafer damage during back grinding of a thin film wafer.

【0002】[0002]

【従来の技術】半導体装置の製造工程では、ウエファ上
に半導体素子領域を形成後、ウエファを所望の仕上げ厚
みにするためにシートに貼り付け、B/G研削を行って
いる。
2. Description of the Related Art In a semiconductor device manufacturing process, after a semiconductor element region is formed on a wafer, the wafer is attached to a sheet so as to have a desired finished thickness, and B / G grinding is performed.

【0003】図5は、従来の半導体装置の製造方法を示
す。
FIG. 5 shows a conventional method of manufacturing a semiconductor device.

【0004】一導電型シリコン半導体基板11表面に酸
化膜および窒化膜12を堆積し、所定のベース領域表面
をエッチングにより露出して逆導電型不純物をイオン注
入後、拡散してベース領域13を形成する。
An oxide film and a nitride film 12 are deposited on the surface of a one conductivity type silicon semiconductor substrate 11, a predetermined base region surface is exposed by etching, and a reverse conductivity type impurity is ion-implanted and then diffused to form a base region 13. I do.

【0005】ベース領域13表面の所定のエミッタ領域
部分を再度エッチングにより露出して一導電型不純物を
付着後、拡散してエミッタ領域14を形成する。
A predetermined emitter region portion on the surface of the base region 13 is exposed again by etching, an impurity of one conductivity type is attached, and then diffused to form an emitter region 14.

【0006】ベース領域13およびエミッタ領域14に
コンタクト孔を設け、金属を付着して所望の電極形状に
なるようにエッチングしてベース電極17及びエミッタ
電極18を形成する。
[0006] Contact holes are provided in the base region 13 and the emitter region 14, and a metal is adhered thereto and etched into a desired electrode shape to form a base electrode 17 and an emitter electrode 18.

【0007】半導体基板11裏面をB/G研削し、例え
ば150μm、200μmなどの所望の仕上げ厚みとし、裏面
に真空蒸着により金属を付着してコレクタ電極(図示せ
ず)とする。
The back surface of the semiconductor substrate 11 is subjected to B / G grinding to a desired finished thickness of, for example, 150 μm or 200 μm, and a metal is attached to the back surface by vacuum evaporation to form a collector electrode (not shown).

【0008】[0008]

【発明が解決しようとする課題】近年パッケージの厚み
を薄くする要求が増えており、今後その対応として更に
ウエファを薄膜化し、高効率および低ロスの半導体装置
の製造が望まれている。
In recent years, there has been an increasing demand for thinner packages, and in order to cope with the demand, it is desired to further reduce the thickness of wafers and to manufacture semiconductor devices with high efficiency and low loss.

【0009】しかしウエファ仕上げ厚みを現在の主流で
ある150μmより更に薄くするようB/G研削を行う
と、ウエファ割れが多発する問題がある。これは各熱処
理工程での熱歪みや窒化膜の線膨張係数の違いからウエ
ファの反りが増大するためで、この反りのためにB/G
研削で真空チャックへの密着性が弱まり特にウエファ外
周で研削時にウエファが上下にばたつくことにより割れ
が発生したり、MPC作業時も真空チャックに密着性が
弱まるために割れが発生する。
However, if B / G grinding is performed so that the finished thickness of the wafer is thinner than the current mainstream of 150 μm, there is a problem that wafer cracking occurs frequently. This is because the warpage of the wafer increases due to the difference in the thermal expansion and the coefficient of linear expansion of the nitride film in each heat treatment step.
Adhesion to the vacuum chuck is weakened by grinding, and cracks occur due to the wafer fluttering up and down during grinding, particularly at the periphery of the wafer, and cracks also occur during MPC work due to weak adhesion to the vacuum chuck.

【0010】[0010]

【課題を解決するための手段】本発明は、かかる課題に
鑑みてなされ、半導体素子領域形成後、ウエファ裏面を
研削して所望の仕上げ厚みにする半導体装置の製造方法
において、ダイシングストリートに溝を設けて前記研削
をすることを特徴とするもので、ダイシングストリート
部分をプラズマ処理によりエッチングして1〜10μm
の深さの溝を設けることによりウエファの反りを低減
し、B/G研削時の真空チャックとウエファの密着性を
高めてダメージ不良を大幅に低減するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a method of manufacturing a semiconductor device having a desired finished thickness by grinding a back surface of a wafer after a semiconductor element region is formed. The dicing street portion is etched by plasma processing to 1 to 10 μm.
By providing a groove having a depth of not more than one, the warpage of the wafer is reduced, and the adhesion between the vacuum chuck and the wafer during B / G grinding is increased to greatly reduce damage defects.

【0011】[0011]

【発明の実施の形態】本発明の半導体装置の製造方法
は、半導体素子領域形成後、ウエファ裏面を研削して所
望の仕上げ厚みにする半導体装置の製造方法において、
ダイシングストリートに溝を設けて前記研削をするもの
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device having a desired finished thickness by grinding a back surface of a wafer after forming a semiconductor element region.
The grinding is performed by providing a groove in the dicing street.

【0012】図1から図4に本発明の実施の形態を詳細
に説明する。
An embodiment of the present invention will be described in detail with reference to FIGS.

【0013】図1は半導体素子領域形成後のウエファの
断面図を示す。
FIG. 1 is a sectional view of a wafer after a semiconductor element region is formed.

【0014】一導電型シリコン半導体基板1表面に酸化
膜および窒化膜2を堆積し、所定のベース領域表面をエ
ッチングにより露出して逆導電型不純物をイオン注入
後、拡散してベース領域3を形成する。
An oxide film and a nitride film 2 are deposited on the surface of a one conductivity type silicon semiconductor substrate 1, a predetermined base region surface is exposed by etching, and a reverse conductivity type impurity is ion-implanted and then diffused to form a base region 3. I do.

【0015】ベース領域3表面の所定のエミッタ領域部
分を再度エッチングにより露出して一導電型不純物を付
着後、拡散してエミッタ領域4を形成する。
A predetermined emitter region portion on the surface of the base region 3 is again exposed by etching, an impurity of one conductivity type is attached, and then diffused to form an emitter region 4.

【0016】ベース領域3およびエミッタ領域4にコン
タクト孔を設け、金属を付着して所望の電極形状になる
ようにレジスト膜5によるマスクをかけ、エッチングし
てベース電極7及びエミッタ電極8を形成する。この
後、レジスト膜5を残したまま次工程の処理を行う。
Contact holes are provided in the base region 3 and the emitter region 4, a metal is adhered, a mask is formed with a resist film 5 so as to have a desired electrode shape, and etching is performed to form a base electrode 7 and an emitter electrode 8. . Thereafter, the next process is performed while the resist film 5 is left.

【0017】図2および図3は本発明の特徴であるダイ
シングストリートに沿って溝を設けて、B/G研削をす
る工程を示す。
FIGS. 2 and 3 show a process of B / G grinding by forming a groove along a dicing street which is a feature of the present invention.

【0018】図2は、ダイシングストリート9が露出す
るようにレジスト膜5のマスクを半導体基板全面に設け
て、プラズマ処理により半導体基板をエッチングして、
深さ1〜10μmの溝10をダイシングストリート9上
に設ける。
FIG. 2 shows that the mask of the resist film 5 is provided on the entire surface of the semiconductor substrate so that the dicing street 9 is exposed, and the semiconductor substrate is etched by plasma processing.
A groove 10 having a depth of 1 to 10 μm is provided on the dicing street 9.

【0019】この溝10を設けることにより、ウエファ
割れが大幅に低減できる。これは、おそらく各熱処理工
程での熱歪みや窒化膜の線膨張係数の違いからウエファ
に発生する反りの原因である引張り応力がこの溝10に
より分断されるためと推測される。
The provision of the groove 10 can greatly reduce wafer cracking. This is presumed to be because the tensile stress, which is a cause of warpage generated in the wafer, is divided by the groove 10 due to the difference in the thermal expansion and the coefficient of linear expansion of the nitride film in each heat treatment step.

【0020】このダイシングストリート9は後の組立工
程で半導体素子を個々に分割(ダイシング)するための
領域なので、この段階で溝10を設けても何ら影響はな
い。ただし、理由は後述するが、溝10の深さは1μm
以上10μm以下が望ましい。
Since the dicing street 9 is a region for individually dividing (dicing) the semiconductor element in a later assembling process, providing the groove 10 at this stage has no effect. However, the depth of the groove 10 is 1 μm
The thickness is preferably 10 μm or more and 10 μm or less.

【0021】図3はレジスト膜を除去して裏面をB/G
研削する工程を示す。
FIG. 3 shows that the resist film is removed and the back surface is B / G
This shows the step of grinding.

【0022】表面のレジスト膜5を除去して表面に保護
用のシートを張り、所望の仕上げ厚みになるように半導
体基板1裏面をB/G研削する。前記のように、ダイシ
ングストリート9に設けた溝10により反りの原因であ
る引っ張り応力が分断されるため、半導体素子領域の形
成工程で、窒化膜の線膨張係数の違いや各熱処理工程で
の熱歪みにより、ウエファに反りが生じていてもB/G
研削前にこの反りが低減できる。
The resist film 5 on the front surface is removed, a protective sheet is put on the front surface, and the back surface of the semiconductor substrate 1 is B / G ground to a desired finished thickness. As described above, since the tensile stress, which is a cause of warpage, is divided by the groove 10 provided in the dicing street 9, the difference in the coefficient of linear expansion of the nitride film and the heat in each heat treatment step are formed in the step of forming the semiconductor element region. B / G even if the wafer is warped due to distortion
This warpage can be reduced before grinding.

【0023】これにより、B/G研削のテーブルとウエ
ファの密着性が良くなり、ウエファ仕上げ厚みを従来よ
り薄くしてもウエファ割れや、ダメージによる不良が大
幅に低減できる。
As a result, the adhesiveness between the B / G grinding table and the wafer is improved, and even if the finished thickness of the wafer is made thinner than before, wafer cracking and defects due to damage can be greatly reduced.

【0024】その後、裏面に真空蒸着により金属を付着
してコレクタ電極(図示せず)とする。
Thereafter, a metal is adhered to the back surface by vacuum evaporation to form a collector electrode (not shown).

【0025】本発明の製造方法による特徴は、ダイシン
グストリート上をプラズマエッチングして深さ1〜10
μmの溝を設けた後、B/G研削することにある。
The feature of the manufacturing method of the present invention is that plasma etching is performed on
After providing a groove of μm, B / G grinding is performed.

【0026】この溝10により、これまでの半導体素子
領域を形成する工程で、窒化膜の線膨張係数の違いや各
熱処理工程での熱歪みなどからウエファに反りが生じて
いても、その反りの原因である引っ張り応力が分断さ
れ、B/G研削前に反りが低減できる。
Due to the groove 10, even if the wafer is warped due to a difference in linear expansion coefficient of the nitride film or thermal distortion in each heat treatment step in the process of forming the semiconductor element region up to now, the warpage is not affected. The tensile stress which is the cause is divided, and the warpage can be reduced before B / G grinding.

【0027】従って、B/G研削のテーブルとウエファ
の密着性が良くなり、ウエファ仕上げ厚みを従来より薄
くなるように研削してもウエファ割れや、ダメージによ
る不良が大幅に低減できる。
Accordingly, the adhesiveness between the B / G grinding table and the wafer is improved, and even if the wafer is ground so that the finished thickness of the wafer becomes thinner than before, the wafer cracking and defects due to damage can be greatly reduced.

【0028】ここで、図4に示すウエファ割れ不良率の
表を参照して溝10の深さを1〜10μmとする理由を
説明する。この表は、プラズマエッチによる溝10の深
さを変えてウエファの仕上げ厚み毎の不良率を測定した
ものである。
Here, the reason why the depth of the groove 10 is set to 1 to 10 μm will be described with reference to a table of wafer cracking defective rates shown in FIG. This table is obtained by measuring the defect rate for each finished thickness of the wafer by changing the depth of the groove 10 due to the plasma etching.

【0029】まず、図4に示すように、溝10が1μm
では、ウエファ仕上げ厚み120μmでの不良率が1%程
度であるが、溝を設けない(0μm)場合は、ウエファ
仕上げ厚み1 20μmでの不良率が大きくなる。これは、
溝10の深さが1μmより浅いと、前記の引っ張り応力
を十分に分断できず、この状態でB/G研削し、その後
に裏面に施す金属蒸着でさらに反りが大きくなると、ウ
エファ仕上げ厚みが従来より薄くなっているために、ウ
エファの機械的強度が弱くなるためである。
First, as shown in FIG.
In this example, the defect rate at a wafer finished thickness of 120 μm is about 1%, but when no groove is provided (0 μm), the defect rate at a wafer finished thickness of 120 μm increases. this is,
If the depth of the groove 10 is less than 1 μm, the tensile stress cannot be sufficiently divided. In this state, if the B / G grinding is performed and the metal deposition applied to the back surface further increases the warp, the thickness of the finished wafer is reduced. This is because the mechanical strength of the wafer is reduced due to the thinner.

【0030】つまり、溝10が1μmより浅い場合に
は、現在主流である150μmの厚みでは問題ないが、ウ
エファ薄膜化を進めると、ウエファ上のいたる場所で割
れが発生することになる。
That is, when the groove 10 is shallower than 1 μm, there is no problem with the thickness of 150 μm, which is currently the mainstream. However, as the wafer becomes thinner, cracks occur everywhere on the wafer.

【0031】一方、溝10の深さが10μmではウエフ
ァ仕上げ厚みが120μmで不良率が1%弱であるが、溝
10の深さが15μmとなると、ウエファ仕上げ厚みが
130μm以下での不良率が増大する。これは、ウエファ
に反りが生じたときに溝10自身から割れが生じたり、
B/G研削工程で貼り付けるシートと溝10の隙間の接
着剤にB/G研削時の水が進入することによりシートが
剥がれ、研削時にウエファが固定できなくなるため割れ
が多発することになる。また、ウエファに対して深い溝
10を多数設けることによりウエファの強度が弱まり、
裏面の金属蒸着時のハンドリングで割れが発生するなど
不良が増大するためである。
On the other hand, when the depth of the groove 10 is 10 μm, the wafer finished thickness is 120 μm and the defect rate is less than 1%, but when the depth of the groove 10 is 15 μm, the wafer finished thickness is reduced.
The defect rate at 130 μm or less increases. This is because when the wafer is warped, a crack is generated from the groove 10 itself,
When the water at the time of B / G grinding enters the adhesive in the gap between the sheet and the groove 10 to be bonded in the B / G grinding step, the sheet is peeled off, and the wafer cannot be fixed at the time of grinding, so that cracks occur frequently. Also, by providing a large number of deep grooves 10 in the wafer, the strength of the wafer is reduced,
This is because defects such as cracks generated during handling during metal deposition on the back surface increase.

【0032】また、溝10の深さが2μmおよび5μm
では、ウエファ不良率が0%となる結果が得られてい
る。
The depth of the groove 10 is 2 μm and 5 μm.
In this example, the result that the wafer defect rate is 0% is obtained.

【0033】以上のことからウエファ割れを防止する溝
10の深さは1〜10μmが望ましいと言える。
From the above, it can be said that the depth of the groove 10 for preventing the wafer crack is preferably 1 to 10 μm.

【0034】[0034]

【発明の効果】本発明によれば、ダイシングストリート
上をプラズマエッチングして溝を設けたのちB/G研削
することにより、ウエファ割れや、ダメージによる不良
を大幅に低減できる。
According to the present invention, by performing B / G grinding after forming a groove by performing plasma etching on the dicing street, defects due to wafer cracking and damage can be greatly reduced.

【0035】半導体素子領域形成後に、ダイシングスト
リート上をプラズマ処理によりエッチングして溝を設け
る。この溝により、これまでの半導体素子領域を形成す
る工程で、窒化膜の線膨張係数の違いや各熱処理工程で
の熱歪みなどからウエファに反りが生じていても、反り
の原因である引っ張り応力が分断され、B/G研削前に
反りが低減できる。
After forming the semiconductor element region, grooves are formed by etching the dicing streets by plasma processing. Even if the wafer is warped due to the difference in the coefficient of linear expansion of the nitride film and the thermal strain in each heat treatment step in the process of forming the semiconductor element region up to now, even if the wafer is warped, the tensile stress causing the warp is generated. , And warpage can be reduced before B / G grinding.

【0036】従って、B/G研削のテーブルとウエファ
の密着性が良くなり、従来よりもウエファ仕上げ厚みを
薄くなるように研削しても、ウエファ割れや、ダメージ
による不良を大幅に低減できる。
Therefore, the adhesion between the B / G grinding table and the wafer is improved, and even if grinding is performed so that the finished thickness of the wafer is smaller than in the past, defects due to wafer cracking and damage can be significantly reduced.

【0037】具体的には、プラズマエッチ量(深さ)が
1〜10μmであれば、ウエファ仕上げ厚みを120μm
にしても、ウエファ割れ不良率が多くても1%前後とい
う効果が得られている。
Specifically, if the plasma etching amount (depth) is 1 to 10 μm, the wafer finished thickness is 120 μm.
However, the effect of about 1% is obtained even if the wafer cracking defect rate is large.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の製造方法を説明するため
の断面図である
FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the present invention.

【図2】本発明の半導体装置の製造方法を説明するため
の断面図である。
FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.

【図3】本発明の半導体装置の製造方法を説明するため
の断面図である。
FIG. 3 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.

【図4】本発明の半導体装置の製造方法を説明するため
の概念図である。
FIG. 4 is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

【図5】従来の半導体装置の製造方法を説明するための
断面図である。
FIG. 5 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子領域形成後、ウエファ裏面を
研削して所望の仕上げ厚みにする半導体装置の製造方法
において、ダイシングストリートに溝を設けて前記研削
をすることを特徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device, comprising: forming a semiconductor element region; and grinding the back surface of the wafer to a desired finished thickness by providing a groove in a dicing street and performing the grinding. Method.
【請求項2】 前記溝はプラズマエッチングにより前記
半導体素子の不純物拡散領域より深く設けることを特徴
とする請求項1に記載の半導体装置の製造方法。
2. The method according to claim 1, wherein the groove is formed deeper than an impurity diffusion region of the semiconductor element by plasma etching.
【請求項3】 前記溝の深さは1μm以上10μm以下
に設けることを特徴とする請求項2に記載の半導体装置
の製造方法。
3. The method for manufacturing a semiconductor device according to claim 2, wherein the depth of the groove is provided to be 1 μm or more and 10 μm or less.
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Cited By (6)

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Publication number Priority date Publication date Assignee Title
EP1528591A2 (en) * 2003-10-30 2005-05-04 Sumitomo Electric Industries, Ltd. Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate
JP2008227521A (en) * 2008-04-07 2008-09-25 Renesas Technology Corp Semiconductor wafer and method for manufacturing semiconductor device
JP2009504432A (en) * 2005-08-06 2009-02-05 イェーノプティク アウトマティジールングステヒニーク ゲゼルシャフト ミット ベシュレンクテル ハフツング A method of tearing a fragile flat member with a laser beam using a previously created trace
US8928121B2 (en) 2007-11-12 2015-01-06 Nxp B.V. Thermal stress reduction
JP2017204653A (en) * 2012-01-27 2017-11-16 ローム株式会社 Method for manufacturing chip resistor
US10483188B2 (en) 2015-12-15 2019-11-19 Commissariat à l'Energie Atomique et aux Energies Alternatives Compensation of an arc curvature generated in a wafer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1528591A2 (en) * 2003-10-30 2005-05-04 Sumitomo Electric Industries, Ltd. Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate
EP1528591A3 (en) * 2003-10-30 2007-03-28 Sumitomo Electric Industries, Ltd. Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate
US7229926B2 (en) 2003-10-30 2007-06-12 Sumitomo Electric Industries, Ltd. Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate
JP2009504432A (en) * 2005-08-06 2009-02-05 イェーノプティク アウトマティジールングステヒニーク ゲゼルシャフト ミット ベシュレンクテル ハフツング A method of tearing a fragile flat member with a laser beam using a previously created trace
US8928121B2 (en) 2007-11-12 2015-01-06 Nxp B.V. Thermal stress reduction
JP2008227521A (en) * 2008-04-07 2008-09-25 Renesas Technology Corp Semiconductor wafer and method for manufacturing semiconductor device
JP4724729B2 (en) * 2008-04-07 2011-07-13 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2017204653A (en) * 2012-01-27 2017-11-16 ローム株式会社 Method for manufacturing chip resistor
US10483188B2 (en) 2015-12-15 2019-11-19 Commissariat à l'Energie Atomique et aux Energies Alternatives Compensation of an arc curvature generated in a wafer

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