JP5034488B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of thinning a semiconductor wafer.

  Conventionally, a method for thinning a semiconductor wafer has been proposed in Patent Document 1, for example. Specifically, in Patent Document 1, after a semiconductor element is formed on the surface side of a semiconductor wafer, one surface of a double-sided tape is pasted on the surface of the semiconductor wafer, and the other surface of the double-sided tape is adhesive and has light. A photothermal conversion layer containing an absorbent and a thermally decomposable resin is attached. Further, a laminated body is prepared by attaching a glass plate as a light transmissive support to the light-to-heat conversion layer.

Subsequently, the back surface of the semiconductor wafer is thinned to a desired thickness. Then, the laser light is transmitted through the glass plate, and the photothermal conversion layer is irradiated with the laser light. As a result, the energy of the laser beam is absorbed by the light absorber and converted into thermal energy. This thermal energy raises the temperature of the light-to-heat conversion layer, causing the heat-decomposable resin to thermally decompose, and foams the resin to generate voids in the light-to-heat conversion layer. Thereby, a semiconductor wafer and a glass plate are isolate | separated. Thereafter, the double-sided tape is peeled off from the surface of the semiconductor wafer. Thus, the semiconductor wafer can be thinned.
JP 2004-64040 A

  However, in the above conventional technique, when the double-sided tape is peeled off from the surface of the semiconductor wafer, the adhesive adheres to the pattern surface due to the influence of the laser or the bubble of the adhesive, and the adhesive remains, so that the surface of the semiconductor wafer is removed. The cleanliness is reduced. For this reason, when a metal layer for the electrode of the semiconductor element is formed on the surface side of the semiconductor wafer after the thinning process of the semiconductor wafer, the metal layer does not grow in the portion where the remaining adhesive is fixed, and a uniform metal layer is formed. There is a problem that it cannot be formed.

  Further, the semiconductor wafer is warped due to the thinning of the semiconductor wafer. As a result, the semiconductor wafer cannot be heated uniformly in the subsequent processes, the problem that the focus is not adjusted due to the warp of the semiconductor wafer during patterning, and the case where the semiconductor wafer is stored or transported to the manufacturing apparatus. There are problems that the semiconductor wafer breaks and that the wafer surface is damaged by contact marks caused by the transfer arm coming into direct contact with the surface of the semiconductor wafer.

  In view of the above points, the present invention has a first object of ensuring the cleanliness of the surface of the semiconductor wafer after the thinning process when the back surface of the semiconductor wafer is thinned, and even if the semiconductor wafer is warped. A second object is to uniformly process a semiconductor wafer, and a third object is to prevent the semiconductor wafer from cracking due to warpage of the semiconductor wafer.

  In order to achieve the above object, according to a first feature of the present invention, a semiconductor wafer structure (30) having a semiconductor element structure and an upper layer (16, 17, 18) formed thereon is prepared. A surface resist (31) is formed on the substrate. Subsequently, a tape member (40) is attached to the surface resist, the semiconductor wafer is fixed to the tape member, and the back surface of the semiconductor wafer is thinned. Thereafter, the tape member is removed from the surface resist, the semiconductor wafer is warped so that the back surface of the semiconductor wafer becomes a convex surface by the film stress of the surface resist, and a back surface structure is formed on the back surface side of the warped semiconductor wafer. To do.

  As a result, it is possible to prevent the processing waste and the adhesive of the tape member from being attached to the upper layer of the semiconductor wafer during thinning, and the cleanliness of the surface side of the semiconductor wafer can be ensured. Further, when the semiconductor wafer is lifted and moved by the transfer arm in order to carry out each step, the surface resist surface of the semiconductor wafer can be lifted by the transfer arm, and the transfer arm is directly attached to the surface of the semiconductor wafer, that is, the upper layer. It can be made not to contact. Thereby, it is possible to prevent the transfer arm from being contacted with the upper layer of the semiconductor wafer.

  And the curvature of a semiconductor wafer can be controlled by the film | membrane stress of a surface resist, and the crack of a semiconductor wafer can be prevented.

  In such a case, when forming the back surface structure, the surface resist is opposed to the installation surface so that the back surface of the semiconductor wafer is convex with respect to the installation surface of the stage (50) provided with the plurality of through holes (51). Then, by sucking air between the stage and the semiconductor wafer from the through hole, the warped semiconductor wafer can be brought into close contact with the installation surface of the stage and flattened.

  Thereby, a back surface can be processed uniformly in the state which flattened the back surface of the semiconductor wafer. Further, since the surface resist is provided on the surface side of the semiconductor wafer, the upper layer of the semiconductor wafer does not directly contact the stage and can be prevented from being damaged.

  In the second feature of the present invention, a surface resist (31) is formed on an upper layer (16, 17, 18) of a prepared semiconductor wafer (30), and a plate is formed on the surface resist via an adhesive (61). A support substrate (60) having a shape is attached and a semiconductor wafer is fixed to the support substrate. Then, the back surface of the semiconductor wafer is thinned. Thereafter, a back surface structure is formed on the back surface side of the semiconductor wafer to which the support substrate is attached.

  Thereby, the warp generated in the thinned semiconductor wafer can be flattened by the support substrate, and the semiconductor wafer can be prevented from being broken by the warp after the thinning. In addition, since the semiconductor wafer is fixed to the support substrate via the surface resist, the surface of the semiconductor wafer can be protected and a cleanliness can be ensured.

  Even in such a case, since the warp of the semiconductor wafer is flattened by the support substrate, the back surface of the semiconductor wafer can be processed uniformly.

  Further, when the back surface structure is formed, a step of forming a back surface resist (32) on the back surface of the semiconductor wafer is included. In the step of forming the back surface resist, the surface is based on the surface of the uppermost layer of the upper layer. When the resist thickness is a and the back resist thickness is b, it is preferable to form the back resist so as to satisfy the condition of a> b.

  In the step of removing the backside resist, it is preferable to remove the surface resist by the thickness of the backside resist by removing the backside resist simultaneously with the removal of the backside resist. As a result, a surface resist having a thickness of ab can be left on the surface side of the semiconductor wafer, and the warp direction and the amount of warpage of the semiconductor wafer before the backside resist removal can be maintained by the surface resist of this thickness. .

  That is, if only the back resist is removed and the front resist is not removed at all, the warpage of the semiconductor wafer must be controlled only by the film stress of the front resist, and the warpage amount is larger than before removing the back resist. There is a risk that the semiconductor wafer will be cracked, but by removing the surface resist portion along with the removal of the back surface resist, the film stress of the surface resist can be relaxed, and the semiconductor wafer can be prevented from cracking. it can.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The semiconductor device shown in the present invention is a semiconductor device provided with a semiconductor element such as an FWD built-in FS-IGBT.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. The surface structure of the semiconductor device shown in this figure is that a channel P-type base layer 11 is formed on the surface layer portion of an N− type drift layer 10 that is a silicon substrate, and an N + type source layer is formed on the surface layer portion of the channel P-type base layer 11. 12 is formed.

Further, a trench 13 is formed so as to penetrate the N + type source layer 12 and the channel P type base layer 11 to reach the N− type drift layer 10, and a gate insulation made of SiO ₂ is formed on the inner wall surface of the trench 13. A film 14 and a gate layer 15 made of PolySi are sequentially formed, and a trench gate structure including the trench 13, the gate insulating film 14, and the gate layer 15 is formed.

  A part of the N + type source layer 12 and the trench gate structure are covered with an insulating layer 16. A surface electrode 17 is formed on the surface of the N− type drift layer 10 in which the trench gate structure is formed so as to contact the channel P type base layer 11 and the N + type source layer 12 so as to straddle the plurality of trench gate structures. A large number of IGBTs are connected in common. The surface electrode 17 functions as a source electrode of the IGBT.

  A protective film 18 is formed at the end of the surface electrode 17. The protective film 18 is patterned so that a portion to be a soldering portion of the surface electrode 17 is opened, and covers the portion other than the soldering portion. As such a protective film 18, for example, polyimide is employed.

  The insulating layer 16, the surface electrode 17, and the protective film 18 are provided above the N− type drift layer 10 that is a silicon substrate, and correspond to the upper layer of the present invention.

  The back surface structure of the semiconductor device has a form in which an N + type layer 19 and a P + type layer 20 are formed on the back surface of the N − type drift layer 10 which is a silicon substrate. The N + type layer 19 and the P + type layer 20 serve as a collector layer in which the IGBT functions as an FS (Field stop) type. The N + type layer 19 and the P + type layer 20 can reduce the thickness of the N− type drift layer 10 which is a silicon substrate, and can obtain favorable characteristics such as the on-voltage and breakdown voltage of the IGBT.

  Further, the P + type layer 20 is provided with an N + type region 21 reaching the N + type layer 19. The N + type region 21 functions as a FWD (free wheel diode) together with the P + type layer 20. A back electrode 22 is formed on the surface of the P + type layer 20 by sputtering. The back electrode 22 functions as an IGBT collector electrode. The above is the overall configuration of the semiconductor device according to the present embodiment.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2 and 4 are views showing a method of manufacturing the semiconductor device shown in FIG. 2 and 4 show the semiconductor element structure shown in FIG. 1 as a cross section of the semiconductor wafer 30.

  First, in the process shown in FIG. 2A, an N− type semiconductor wafer 30 as an FZ wafer is prepared with a thickness of, for example, 400 μm or more, and the trench shown in FIG. A gate structure is formed. Then, an insulating film is formed on the surface of the semiconductor wafer 30 and patterned. Thereby, the insulating layer 16 is formed, the contact hole is provided, and the surface electrode 17 made of Al is formed. Thereafter, a protective film 18 made of polyimide is patterned on the surface of the semiconductor wafer 30.

  In the step shown in FIG. 2B, a surface resist 31 is applied on the semiconductor wafer 30. The surface resist 31 is for preventing the surface of the semiconductor wafer 30 from being damaged by the contact between the particles and the manufacturing apparatus and the semiconductor wafer 30 in the subsequent process. In this step, a positive resist is employed as the surface resist 31, and the thickness of the thinnest part is 3.5 μm.

  Here, the thickness of the surface resist 31 based on the surface of the protective film 18 farthest from the surface of the semiconductor wafer 30 is defined as a. Therefore, the thickness a of the surface resist 31 is 3.5 μm. When the surface resist 31 is applied to the semiconductor wafer 30 in this way, the semiconductor wafer 30 is warped by the stress of the surface resist 31. That is, the warp of the semiconductor wafer 30 can be controlled by the thickness a of the surface resist 31.

  In this step, the surface resist 31 is provided so that the back surface of the semiconductor wafer 30 is convex by the surface resist 31. That is, the back surface of the semiconductor wafer 30 is convex. Accordingly, the surface of the semiconductor wafer 30 becomes concave.

  As described above, if the warpage of the semiconductor wafer 30 can be controlled to be constant by the surface resist 31, when the semiconductor wafer 30 is taken out of the transfer case, the warped semiconductor wafer 30 installed in the transfer case is taken into consideration. The height can be set in advance. As a result, it is possible to avoid the problem that the semiconductor wafer 30 is cracked when the semiconductor wafer 30 is transported to a transport case or a manufacturing apparatus.

  In the step shown in FIG. 2C, the semiconductor wafer 30 is thinned. Specifically, a grind tape 40 is attached to the surface side of the semiconductor wafer 30 on which the surface resist 31 is formed, and back grinding is performed. In this step, the semiconductor wafer 30 is thinned to 200 μm or less. At this time, Si debris of the semiconductor wafer 30 adheres to the grind tape 40, but the Si debris on the surface side of the semiconductor wafer 30 is removed together with the grind tape 40 by peeling the grind tape 40. The grind tape 40 corresponds to the tape member of the present invention.

  Thereafter, the surface resist 31 on the semiconductor wafer 30 is washed with running water to remove the remaining adhesive on the surface resist 31. Subsequently, the back surface of the semiconductor wafer 30 is etched by single wafer wet etching to finish the mirror surface. At this time, since the surface resist 31 is applied to the surface side of the semiconductor wafer 30, even if the surface resist 31 of the semiconductor wafer 30 contacts the transfer arm or stage of the manufacturing apparatus, the surface of the semiconductor wafer 30 is not damaged. .

  In the step shown in FIG. 2D, ion implantation is performed on the back surface of the semiconductor wafer 30 to form an FS layer. In order to perform this step, the semiconductor wafer 30 that has completed the step shown in FIG. 2C is placed on a transfer arm and moved to a device that performs ion implantation.

  FIG. 3 is a diagram schematically showing a stage on which the semiconductor wafer 30 is arranged. As shown in this figure, the semiconductor wafer 30 is placed on the surface of the stage 50. At this time, the semiconductor wafer 30 is arranged so that the surface of the semiconductor wafer 30 faces the surface of the stage 50. As a result, as shown in FIG. 3, a space is formed between the surface of the stage 50 and the surface of the semiconductor wafer 30.

  The stage 50 is provided with a plurality of through holes 51, and the pipes 52 connected to the through holes 51 from the back surface of the stage 50 are connected to the vacuum pump 53. Then, by driving the vacuum pump 53, the air between the stage 50 and the semiconductor wafer 30 is sucked in, the surface of the semiconductor wafer 30 is brought into close contact with the surface of the stage 50, and the warp of the semiconductor wafer 30 is eliminated. Thereby, the semiconductor wafer 30 can be heated uniformly. In order to eliminate the warp of the semiconductor wafer 30 and perform each process, the stage 50 shown in FIG. 3 is also used in the following processes.

Then, ion implantation is performed with the semiconductor wafer 30 in close contact with the stage 50. In this step, phosphorus is ion-implanted at a high acceleration of 500 keV or more at a dose of 1 × 10 ¹² cm ⁻² or more to form the N + type layer 19 on the back surface of the semiconductor wafer 30, and then the P + type layer 20. Is formed by ion implantation at a dose of 1 × 10 ¹³ cm ⁻² or more.

  In this process, the surface of the semiconductor wafer 30 is held and moved by the transfer arm, but since the surface resist 31 is formed on the surface of the semiconductor wafer 30, the surface resist 31 of the semiconductor wafer 30 is moved to the transfer arm or the destination. It is possible to prevent the surface of the semiconductor wafer 30 from being damaged even if it contacts the stage.

  In addition, when a sheet-like material such as a tape is attached to the surface of the semiconductor wafer 30 instead of the surface resist 31, a gap is generated between the semiconductor wafer 30 and the tape due to the unevenness of the surface of the semiconductor wafer 30, and the vacuum state In the ion implantation processing chamber, the air in the gap expands and an adsorption error in the stage 50 occurs. However, when the surface resist 31 is provided when the maximum level difference on the surface of the semiconductor wafer 30 is 10 μm as in the present embodiment, the unevenness on the surface of the semiconductor wafer 30 is sufficiently filled with the surface resist 31, so that the adsorption It was confirmed that there was no error.

  Next, in the step shown in FIG. 4A, a diode region is formed. For this purpose, first, a back surface resist 32 is formed on the back surface of the semiconductor wafer 30. The component of the back resist 32 is preferably etched at the same rate when the front resist 31 is removed, and the same component as the front resist 31 is preferable.

  Further, a back resist 32 thinner than the front resist 31 is formed. That is, when the thickness of the back resist 32 is b, the back resist 32 is formed such that the thickness a of the front resist 31 (thickness of the thinnest portion)> the thickness b of the back resist 32.

  Thereafter, the back resist 32 is patterned to open a portion where the N + type region 21 constituting the FWD is to be formed. In this case, since the semiconductor wafer 30 is flattened on the stage 50, it is possible to solve the problem that the focus is not achieved due to the warp of the semiconductor wafer 30 during patterning.

  The patterning process includes application of the back resist 32, pre-baking, exposure, development, and post-baking. If the condition of the thickness of the front resist 31> the thickness b of the back resist 32 is satisfied, the pre-baking process is performed. The subsequent warpage of the semiconductor wafer 30 becomes a convex state when the back resist 32 is placed upward with respect to the installation surface due to the balance of stress of the resists 31 and 32.

  For example, when the thickness a of the front surface resist 31 is 3.5 μm and the thickness b of the back surface resist 32 is 2.0 μm, the amount of warpage of the semiconductor wafer 30 is approximately 1 mm on the back surface of the semiconductor wafer 30. Even after post-baking, the warping direction and the warping amount of the semiconductor wafer 30 are the same.

  The present inventors obtained the following results from experiments on the optimal warping direction and warping amount for transporting the semiconductor wafer 30 and stage adsorption. First, the warping direction of the semiconductor wafer 30 is preferably such that the back surface of the semiconductor wafer 30 is convex with respect to the surface of the stage 50, and the warping amount is 2 mm or less. Regarding the warping direction of the semiconductor wafer 30, air does not escape from the outer periphery of the semiconductor wafer 30 during stage suction, and tends to be attracted. Further, the upper limit of the warpage amount of the semiconductor wafer 30 is a limit value that does not cause a conveyance error. From such a viewpoint, the warp direction and the warp amount described above are optimal.

  Thus, in this step, even when the back resist 32 is formed on the back surface of the semiconductor wafer 30, the back surface of the semiconductor wafer 30 becomes a convex surface, and the transfer arm contacts the surface resist 31 of the semiconductor wafer 30, etc. The surface of the semiconductor wafer 30 is not damaged, and a stage adsorption error does not occur in the next back surface ion implantation process.

Then, phosphorus is ion-implanted with a dose amount of 5 × 10 ¹³ cm ⁻² or more as a condition for sufficiently repelling the P + type layer 20 to form an N + type region 21 that functions as a cathode of the FWD region.

  In the step shown in FIG. 4B, the back surface resist 32 is removed. In this step, for example, the resists 31 and 32 are stripped at a time on both surfaces of the semiconductor wafer 30 with a barrel-type asher. In this case, as described above, the resists 31 and 32 formed on the front and back surfaces of the semiconductor wafer 30 are such that the thickness a of the front surface resist 31> the thickness b of the back surface resist 32. Even if completely removed, the surface resist 31 having a thickness of ab remains on the surface side of the semiconductor wafer 30.

  The reason why only the back surface resist 32 is removed and the front surface resist 31 is left as it is is to maintain the magnitude of the resist film stress. For example, the thickness a of the front surface resist 31 before removing the back surface resist 32 is 3.5 μm, the thickness b of the back surface resist 32 is 2.0 μm, and the back surface of the semiconductor wafer 30 is convex by about 1 mm. In this case, if only the back surface resist 32 is removed and the front surface resist 31 having a thickness of 3.5 μm is left as it is, the back surface of the semiconductor wafer 30 becomes convex by about 2.5 mm, and an error occurs in the subsequent transport system. Get up.

  On the other hand, as in this step, when both resist surfaces of the semiconductor wafer 30 are peeled off at once to leave a surface resist 31 having a thickness of 1.0 μm, the back surface of the semiconductor wafer 30 is warped by about 1 mm, and each resist 31 , 32 can be maintained in the warp direction and warp amount of the semiconductor wafer 30.

  In the step shown in FIG. 4C, impurities on the back surface of the semiconductor wafer 30 are activated. Also in this step, the stage adsorption error does not occur as described above, and the surface resist 31 remains on the surface of the semiconductor wafer 30, so that even if the surface resist 31 of the semiconductor wafer 30 contacts the transfer arm or the stage 50. The surface of the semiconductor wafer 30 is not damaged.

  Subsequently, the back electrode 22 is formed by sputtering or plating, and the surface resist 31 is removed. The back surface contact in the removal of the front surface resist 31 is in a state in which the back surface electrode 22 is completely formed, and there is no problem because foreign matter and contact traces between the back surface electrode 22 are not generated.

  Thereafter, a metal electrode (not shown) for soldering is formed on the surface electrode 17 by sputtering or plating. Since the transport arm and the stage 50 are not in direct contact with the surface electrode 17 formed in advance, the reliability due to the foreign matter between layers and the transport trace when forming the metal electrode on the surface electrode 17 is not lowered. can do. Then, the semiconductor device shown in FIG. 1 is completed by dividing the semiconductor wafer 30 into individual semiconductor chips by dicing cutting.

  As described above, in this embodiment, the surface resist 31 is formed on the surface of the semiconductor wafer 30 on which the semiconductor element structure is formed, and the semiconductor wafer 30 is warped so that the back surface of the semiconductor wafer 30 is convex. And Thereby, the surface of the surface resist 31 of the semiconductor wafer 30 can be supported and moved by the transfer arm, and the surface of the semiconductor wafer 30 can be prevented from being damaged.

  Further, when the semiconductor wafer 30 is installed so that the surface of the semiconductor wafer 30 is in contact with the stage 50, the surface of the semiconductor wafer 30 can be similarly protected, and the cleanliness of the surface of the semiconductor wafer 30 can be ensured. it can. At this time, since the back surface of the semiconductor wafer 30 is convex with respect to the surface of the stage 50, air between the surface of the stage 50 and the surface of the semiconductor wafer 30 can be easily sucked, and the warp of the semiconductor wafer 30 can be prevented. Can be flattened.

  Then, by removing the surface resist 31 and forming a metal electrode on the surface side of the semiconductor wafer 30, the metal electrode can be uniformly formed on the surface electrode 17 on which no scratches or dust remain.

  In addition, when the back surface structure is formed on the semiconductor wafer 30, the thickness b of the back surface resist 32 is smaller than the thickness a of the surface resist 31. Thus, by simultaneously removing the resists 31 and 32 after the back surface structure is formed, the surface resist 31 can be left on the surface of the semiconductor wafer 30, and the transport traces by the transport arm on the surface of the semiconductor wafer 30 also in the subsequent steps. Can be avoided.

  Furthermore, the warp of the semiconductor wafer 30 after removing the back surface resist 32 can be maintained in a state where the back surface is convex. As a result, the semiconductor wafer 30 can be held and moved by the transfer arm with the surface resist 31 on the ground side. Even in this case, since the transfer arm only contacts the surface resist 31, the surface of the semiconductor wafer 30 can be prevented from being damaged.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. The present embodiment is characterized in that the semiconductor device is manufactured while correcting the warp of the semiconductor wafer 30 with the support substrate.

FIG. 5 is a diagram illustrating manufacturing steps for manufacturing a semiconductor device according to the second embodiment of the present invention. In the present embodiment, first, the surface resist 31 is formed on the semiconductor wafer 30 by performing the steps shown in FIGS. 2 (a) and 2 (b).

  Subsequently, in the process illustrated in FIG. 5, the support substrate 60 is installed on the surface side of the semiconductor wafer 30. Specifically, an adhesive 61 is applied on one side of the support substrate 60, and the surface resist 31 of the semiconductor wafer 30 is attached to the surface of the adhesive 61. Thereby, the warp of the semiconductor wafer 30 caused by the film stress of the surface resist 31 can be flattened by the support substrate 60. As such a support substrate 60, for example, a glass plate is employed.

  Thus, since the semiconductor wafer 30 is firmly fixed by the support substrate 60, when making the back surface of the semiconductor wafer 30 into a thin film, it can be made thinner than the case of the said 1st Embodiment. In the present embodiment, the semiconductor wafer 30 can be thinned to a thickness of 20 μm, for example.

  Thereafter, after the process shown in FIG. 4B is performed, the support substrate 60 is removed from the semiconductor wafer 30. At this time, since the surface resist 31 is formed on the surface of the semiconductor wafer 30, the surface structure of the semiconductor wafer 30 is not damaged. Then, the process shown in FIG. 4C is performed to form a metal electrode (not shown), and the semiconductor wafer 30 is diced to complete the semiconductor device shown in FIG.

  As described above, even when the warp of the semiconductor wafer 30 is corrected by the support substrate 60, the surface of the semiconductor wafer 30 can be protected by forming the surface resist 31 on the surface side of the semiconductor wafer 30 in advance. Can do.

(Other embodiments)
In each of the above embodiments, a resist is formed as the resists 31 and 32 on the semiconductor wafer 30, but other protective films such as a resin may be adopted.

  The structure of the semiconductor element shown in FIG. 1 is an example, and is not limited to this structure. The manufacturing method described in each of the above embodiments is applied to the structure having structures on the front and back surfaces of the semiconductor substrate. Can be adopted.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a manufacturing process for manufacturing the semiconductor device shown in FIG. 1. It is the figure which showed typically the stage which arrange | positions a semiconductor wafer. FIG. 3 is a diagram showing a manufacturing process for manufacturing the semiconductor device following FIG. 2. It is the figure which showed the manufacturing process which manufactures the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 16 ... Insulating layer, 17 ... Surface electrode, 18 ... Protective film, 30 ... Semiconductor wafer, 31 ... Surface resist, 32 ... Backside resist, 40 ... Grind tape, 50 ... Stage, 51 ... Through-hole, 60 ... Support substrate, 61 …adhesive.

Claims (3)

Preparing a semiconductor element structure and an upper layer (16, 17, 18) formed on the surface side of a semiconductor wafer (30), and forming a surface resist (31) on the upper layer;
Attaching the tape member (40) to the surface resist and fixing the semiconductor wafer to the tape member, and thinning the back surface of the semiconductor wafer;
After thinning the back surface of the semiconductor wafer, removing the tape member from the surface resist, and warping the semiconductor wafer so that the back surface of the semiconductor wafer becomes a convex surface by the film stress of the surface resist;
Look including a step of forming a back surface structure on the back side of the warped semiconductor wafer,
In the step of forming the back surface structure, the surface resist is opposed to the installation surface so that the back surface of the semiconductor wafer is convex with respect to the installation surface of the stage (50) provided with a plurality of through holes (51). And a step of drawing the air between the stage and the semiconductor wafer from the through hole so that the warped semiconductor wafer is brought into close contact with the installation surface of the stage and flattened. A manufacturing method comprising:
The step of forming the back surface structure includes a step of forming a back surface resist (32) on the back surface of the semiconductor wafer,
In the step of forming the backside resist, the condition of a> b is satisfied, where a is the thickness of the surface resist based on the uppermost surface of the upper layer, and b is the thickness of the backside resist. The method for manufacturing a semiconductor device is characterized in that the back resist is formed as described above . Preparing a semiconductor element structure and an upper layer (16, 17, 18) formed on the surface side of a semiconductor wafer (30), and forming a surface resist (31) on the upper layer;
Attaching a plate-like support substrate (60) to the surface resist via an adhesive (61), fixing the semiconductor wafer to the support substrate, and thinning the back surface of the semiconductor wafer;
Forming a back surface structure on a back surface side of the semiconductor wafer to which the support substrate is attached, and a manufacturing method of a semiconductor device,
The step of forming the back surface structure includes a step of forming a back surface resist (32) on the back surface of the semiconductor wafer,
In the step of forming the backside resist, the condition of a> b is satisfied, where a is the thickness of the surface resist based on the uppermost surface of the upper layer, and b is the thickness of the backside resist. The method for manufacturing a semiconductor device is characterized in that the back resist is formed as described above . The step of forming the back surface structure includes a step of removing the back surface resist,
3. The method according to claim 1, wherein, in the step of removing the back resist, the front resist is removed by the thickness of the back resist by simultaneously removing the front resist together with the removal of the back resist. A method for manufacturing a semiconductor device.

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