JPS6384141A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6384141A JPS6384141A JP23039286A JP23039286A JPS6384141A JP S6384141 A JPS6384141 A JP S6384141A JP 23039286 A JP23039286 A JP 23039286A JP 23039286 A JP23039286 A JP 23039286A JP S6384141 A JPS6384141 A JP S6384141A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- resist
- metal film
- grinding
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000012044 organic layer Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract 8
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000007853 buffer solution Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000009210 therapy by ultrasound Methods 0.000 abstract description 2
- 230000002411 adverse Effects 0.000 abstract 2
- 238000003754 machining Methods 0.000 abstract 1
- 239000011368 organic material Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 201000001880 Sexual dysfunction Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法、特に、ウェハーの裏面
研削から金属膜蒸着に至る工程の改善に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to an improvement in the process from wafer back grinding to metal film deposition.
従来の技術
第２図の工程フローチャートを参照しながら従来の技術
を説明する。素子の形成、配線、保護膜の成長などの表
面加工を終了したウェハーの表面に、有機物層、たとえ
ば、レジスト層を塗布して、ウェハー表面の微小な凹凸
を埋めて平坦化したのち、裏面研削を行うことがある。Prior Art The conventional technology will be explained with reference to the process flowchart shown in FIG. After surface processing such as element formation, wiring, and protective film growth, an organic layer, such as a resist layer, is applied to the surface of the wafer to fill in minute irregularities on the wafer surface and flatten it, followed by back grinding. may be done.
この時に、有機物層はウェハー表面を保護するためのも
のである。なお、この有機物層の表面に、さらにシート
を貼付する場合もある。次に、表面研削手段、たとえば
、グラインダで裏面を研削してウェハーの厚さを望む値
にする。次に、シートを用いた場合にはシートを剥離し
たのち、ウェハー表面から有機物層も除去する。有機物
層がレジストである場合にはアセトンあるいは発煙硝酸
などの渠品を用いる。続いて研削面に成長した薄い酸化
膜を除去する。これはウェハーと、後で蒸着する金属膜
とのオーミックコンタクトを確実にするためである。ウ
ェハーがシリコンの場合にはたとえばフッ化水素酸を１
〜５％含む緩衝液を用いる。次に研削面に金やアルミニ
ウムなどの金属膜を蒸着する。これはプローブ検査時あ
るいは組立後、ウェハーあるいはチップ裏面からの電位
供給を確実にするためである。At this time, the organic layer is for protecting the wafer surface. Note that a sheet may be further attached to the surface of this organic layer. Next, the back surface is ground with a surface grinding means, for example a grinder, to give the wafer a desired thickness. Next, if a sheet is used, after peeling off the sheet, the organic layer is also removed from the wafer surface. When the organic layer is a resist, a diluted product such as acetone or fuming nitric acid is used. Next, the thin oxide film that has grown on the ground surface is removed. This is to ensure ohmic contact between the wafer and the metal film that will be deposited later. If the wafer is silicon, for example, add 1 portion of hydrofluoric acid.
A buffer containing ~5% is used. Next, a metal film such as gold or aluminum is deposited on the ground surface. This is to ensure that the potential is supplied from the backside of the wafer or chip during probe inspection or after assembly.
発明が解決しようとする問題点
以上述へた従来技術では酸化膜除去の工程において、研
削面の酸化膜のみならず、ウェハー表面のリンガラスな
どの保１１１Ｉやアルミニウム電極が一部エッチングさ
れ、信頼性上の大きな問題となる。Problems to be Solved by the Invention In the prior art described above, in the process of removing the oxide film, not only the oxide film on the grinding surface but also the phosphor glass and aluminum electrodes on the wafer surface are partially etched, resulting in unreliability. It becomes a big sexual problem.
問題点を解決するための手段
このような問題を解決するために、本発明は、ウェハー
表面の有機物層を残した状態で研削面の酸化膜を除去し
、研削面に金属膜を蒸着した後、ウェハー表面の有機物
層を除去する工程をそなえたものである。Means for Solving the Problems In order to solve these problems, the present invention removes the oxide film on the ground surface while leaving the organic layer on the wafer surface, and then deposits a metal film on the ground surface. , which includes a process for removing the organic layer on the wafer surface.
作用
本発明によれば、研削面の酸化膜除去の際にウェハー表
面が有機物層で覆われているので保護膜やアルミニウム
電極が酸化膜除去液でエツチングされることがない。According to the present invention, since the wafer surface is covered with an organic layer when removing the oxide film from the ground surface, the protective film and the aluminum electrode are not etched by the oxide film removing solution.
実施例
第１図を参照しながら本発明の詳細な説明する。表面加
工の終了したウェハーに、有機物層として、レジストを
塗布し、１００〜１５０℃で杓１分間ベーキングを行な
う。レジスト層の厚さはベーキング後１〜３μｍでよい
。次（こ必要に応じて、シートを貼付した後、サーフェ
スグラインダーで裏面を研削し、ウェハーを所定の厚さ
にする。研削が終われば、シートを用いた場合にはシー
トを剥離した後、ウェハー表面側にレジスト層を残した
状態で研削面の酸化膜除去、すなわち、研削面の清浄化
処理を行なう。ウェハーがシリコンの場合には、従来同
様、たとえば、フッ化水素酸を１〜５％含む緩衝液を用
いれば５〜１０秒で研削面の酸化膜は完全に除去される
。この際、ウェハー表面はレジストによって保護されて
いるのでウェハー表面の保護膜やアルミニウム電極はま
ったくエツチングされない。続いて研削面に、金、アル
ミニウムなど、所望の金属膜を蒸着する。次にウェハー
をアセトン中で超音波処理を行なって表面に残っている
レジストを除去する。EMBODIMENT OF THE INVENTION The present invention will be described in detail with reference to FIG. A resist is applied as an organic layer to the surface-treated wafer, and baked at 100 to 150° C. for 1 minute. The thickness of the resist layer may be 1 to 3 μm after baking. Next (if necessary, after pasting the sheet, grind the back side with a surface grinder to make the wafer the desired thickness. Once the grinding is finished, if a sheet is used, peel it off and then grind the wafer. The oxide film on the ground surface is removed with the resist layer left on the surface side, that is, the ground surface is cleaned.If the wafer is silicon, as in the past, for example, 1 to 5% hydrofluoric acid is applied. The oxide film on the ground surface is completely removed in 5 to 10 seconds using a buffer solution containing the wafer.At this time, since the wafer surface is protected by the resist, the protective film and aluminum electrode on the wafer surface are not etched at all.Continued A desired metal film, such as gold or aluminum, is then deposited on the ground surface.The wafer is then subjected to ultrasonic treatment in acetone to remove the resist remaining on the surface.
発明の効果
本発明の半導体装置の製造方法によれば、ウェハーの研
削面の清浄化処理としての酸化膜を除去する際に、ウェ
ハー表面の保護膜やアルミニウム電極がエツチングされ
ることかまった（なく、高信頼性の半導体装置の製造が
可能となる。Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, when removing an oxide film as a cleaning treatment on the ground surface of a wafer, the protective film and aluminum electrode on the wafer surface are not etched. , it becomes possible to manufacture highly reliable semiconductor devices.
第１図は本発明実施例の半導体装置の製造方法を示す工
程フローチャート、第２図は従来技術の製造方法を示す
工程フローチャートである。
代理人の氏名 弁理士 中尾敏男 ほか１名第１図FIG. 1 is a process flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process flowchart showing a manufacturing method of a conventional technique. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1
Claims (1)
裏面側を研削加工し、同裏面に金属膜を形成するに際し
、前記基板の表裏全面を有機物層で被覆する工程、前記
基板の裏面側を、同基板の表面側に前記有機物層を残存
のまま、研削する工程、前記基板裏面側の研削面を清浄
処理したのち、同研削面に金属膜を被着形成する工程お
よび前記基板表面に残存の前記有機物層を除去する工程
を、この記載順に実施することを特徴とする半導体装置
の製造方法。After forming a predetermined element portion on the front side of the substrate, grinding the back side of the substrate and forming a metal film on the back side, a step of coating the entire front and back surfaces of the substrate with an organic layer; a step of grinding the side of the substrate with the organic layer remaining on the front side of the substrate; a step of cleaning the ground surface on the back side of the substrate and then forming a metal film on the ground surface; and a step of forming a metal film on the ground surface of the substrate; A method for manufacturing a semiconductor device, characterized in that the step of removing the organic layer remaining in the semiconductor device is performed in the order described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23039286A JPS6384141A (en) | 1986-09-29 | 1986-09-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23039286A JPS6384141A (en) | 1986-09-29 | 1986-09-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384141A true JPS6384141A (en) | 1988-04-14 |
Family
ID=16907157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23039286A Pending JPS6384141A (en) | 1986-09-29 | 1986-09-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384141A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008159848A (en) * | 2006-12-25 | 2008-07-10 | Denso Corp | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5994821A (en) * | 1982-11-24 | 1984-05-31 | Fuji Electric Co Ltd | Manufacture of semiconductor element |
| JPS61121335A (en) * | 1984-11-16 | 1986-06-09 | Rohm Co Ltd | Processing method for grounding surface of wafer |
-
1986
- 1986-09-29 JP JP23039286A patent/JPS6384141A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5994821A (en) * | 1982-11-24 | 1984-05-31 | Fuji Electric Co Ltd | Manufacture of semiconductor element |
| JPS61121335A (en) * | 1984-11-16 | 1986-06-09 | Rohm Co Ltd | Processing method for grounding surface of wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008159848A (en) * | 2006-12-25 | 2008-07-10 | Denso Corp | Method for manufacturing semiconductor device |
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