JPS5994821A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS5994821A JPS5994821A JP20563682A JP20563682A JPS5994821A JP S5994821 A JPS5994821 A JP S5994821A JP 20563682 A JP20563682 A JP 20563682A JP 20563682 A JP20563682 A JP 20563682A JP S5994821 A JPS5994821 A JP S5994821A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- electrode
- pitch
- film
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
本発明は半導体基板の一面の全面と他面の所定の領域に
電極を有する半導体素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor element having electrodes on the entire surface of one surface of a semiconductor substrate and in a predetermined region on the other surface.
例えばプレーナ型半導体素子の製造の場合、一般に素子
の表面側の管理に比べ、裏面側の管理は粗雑に扱われが
ちである。しかしウエーノ・工程中実面が支持台などか
ら汚染される等の問題があり、裏面電極の被着後電極の
剥離が起きるなど半導体基板と電極との間の密着に対し
て悪い影響を及ぼす。For example, in the case of manufacturing planar semiconductor devices, the back side of the device generally tends to be managed more roughly than the front side of the device. However, there are problems such as contamination of the solid surface of the wafer from the support stand, etc., and adverse effects on the adhesion between the semiconductor substrate and the electrode, such as peeling of the electrode after the back electrode is attached.
本発明は、上述の欠点を除去して表面電極のみならず裏
面電極も密着性が良好で安定している半導体素子を製造
する方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor element in which not only the front electrode but also the back electrode have good and stable adhesion by eliminating the above-mentioned drawbacks.
この目的は、−面の全面に高濃度不純物含有層を有する
半導体基板の両面に酸化膜を被覆し、他面の酸化膜の所
定の領域を除去し、その領域に不純物を拡散せしめたの
ち一面の酸化膜を除去し、−面および前記領域の他面に
電極を被着することによって達成される。The purpose of this is to coat both sides of a semiconductor substrate with a high concentration impurity-containing layer on the entire negative side, remove a predetermined area of the oxide film on the other side, diffuse impurities into that area, and then coat the entire surface with an oxide film. This is accomplished by removing the oxide film of the area and depositing electrodes on the - side and the other side of the region.
本発明は、従来表面電極形成のために半導体基板の両面
に形成された酸化膜の表面側の所定の領域を除去する際
裏面の酸化膜も同時に除去していたものを、裏面電極形
成の直前まで裏面酸化膜を残して保護用として利用する
との考えに基づいている。In the present invention, the oxide film on the back side was also removed at the same time when removing a predetermined area on the front side of the oxide film formed on both sides of the semiconductor substrate for forming the front electrode. This is based on the idea that the oxide film on the back side is left and used for protection.
以下図を引用して本発明の一実施例について説明する。An embodiment of the present invention will be described below with reference to the drawings.
第1図(A)〜tC)は一枚のシリコン板に多数のPN
接合を形成し、両面に電極を被着したのち分割して多数
のダイオードを製造する工程の一部を示す。第1図体)
に示すように、N形シリコン基板1の一面には全面に高
濃度N+層2が形成されており、さらに両面に例えば熱
酸化法により酸化膜3および4が生成されている。次に
第2図(B)においては、裏面酸化膜4の全面をピッチ
5で被覆し、表面酸化膜3の一部領域をフォトエツチン
グ法により除去する。第2図(C)においては、裏面の
ピ。Figure 1 (A) to tC) shows a large number of PNs on one silicon plate.
A part of the process of forming a junction, depositing electrodes on both sides, and then dividing it to produce a large number of diodes is shown. 1st figure)
As shown in FIG. 1, a high concentration N+ layer 2 is formed on one surface of an N-type silicon substrate 1, and oxide films 3 and 4 are further formed on both surfaces by, for example, a thermal oxidation method. Next, in FIG. 2(B), the entire surface of the back oxide film 4 is covered with a pitch 5, and a part of the front oxide film 3 is removed by photo-etching. In FIG. 2(C), the pin on the back side.
チ5を除去し、表面酸化膜3の窓から例えばほう素のよ
うな不純物を拡散して2層6を形成し、アルミニウムの
蒸着などによりアノード電極7を被着する。次いで表面
をピッチなどで被覆したのち裏面酸化膜4をエツチング
などで除去し、第2図(Dlに示すようにそのあとヘカ
ソード電極8を設ける。最後に各PN接合相互の中間で
切断すれば、PN接合の露出部を酸化膜3で被覆し、両
面にアノード電極7、カソード電極8を有するプレーナ
型ダイオードチップを多数得ることができる。Then, an impurity such as boron is diffused through the window of the surface oxide film 3 to form a second layer 6, and an anode electrode 7 is deposited by vapor deposition of aluminum or the like. Next, after covering the surface with pitch or the like, the backside oxide film 4 is removed by etching or the like, and then a hecathode electrode 8 is provided as shown in FIG. By covering the exposed portion of the PN junction with the oxide film 3, a large number of planar diode chips having an anode electrode 7 and a cathode electrode 8 on both sides can be obtained.
以上述べたように、本発明は裏面電極形成前まで裏面に
酸化膜を残すことにより、そこ迄の工程中裏面を汚染な
どにより保護することが可能となり、裏面が物理的、化
学・的に安定した状態が保たれるので裏面電極の剥離等
の発生がなく、半導体と電極の接触が非常に良好になる
効果が得られる。As described above, in the present invention, by leaving an oxide film on the back surface before forming the back electrode, it is possible to protect the back surface from contamination during the process up to that point, and the back surface is physically, chemically and stably stabilized. Since this state is maintained, peeling of the back electrode does not occur, and the effect of very good contact between the semiconductor and the electrode can be obtained.
もちろん上記実施例のダイオードに限らず、トランジス
タ、IC等幅広い半導体素子の製造に有効に適用できる
。Of course, the present invention is not limited to the diodes of the above embodiments, but can be effectively applied to the manufacture of a wide variety of semiconductor devices such as transistors and ICs.
第1図゛(A)〜(D)は本発明の一実施例のダイオー
ド製造工程の一部を示す断面図である。
1・・シリコン基板、2・・・N十層、3・4・・・酸
化膜、7・・・表面電極(アノード)、8・・・裏面電
極(カソード)。FIGS. 1(A) to 1(D) are cross-sectional views showing a part of a diode manufacturing process according to an embodiment of the present invention. 1...Silicon substrate, 2...10 N layers, 3.4...Oxide film, 7...Surface electrode (anode), 8...Back surface electrode (cathode).
Claims (1)
を有する半導体素子を製造するに際し、−面の全面に高
濃度不純物含有層を有する半導体基板の両面に酸化膜を
被覆し、他面の酸化膜の所定の領域を除去し、該領域に
不純物を拡散せしめたのち一面の酸化膜を除去し、−面
および前記領域の他面に電極を被着することを特徴とす
る半導体素子の製造方法。1) When manufacturing a semiconductor element having electrodes on the entire surface of one surface of a semiconductor substrate and a predetermined region on the other surface, an oxide film is coated on both surfaces of the semiconductor substrate that has a highly concentrated impurity-containing layer on the entire surface of the negative surface. A semiconductor device characterized in that a predetermined region of an oxide film on a surface is removed, an impurity is diffused into the region, the oxide film on one surface is removed, and an electrode is deposited on the - surface and the other surface of the region. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20563682A JPS5994821A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20563682A JPS5994821A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5994821A true JPS5994821A (en) | 1984-05-31 |
Family
ID=16510168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20563682A Pending JPS5994821A (en) | 1982-11-24 | 1982-11-24 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5994821A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6384141A (en) * | 1986-09-29 | 1988-04-14 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1982
- 1982-11-24 JP JP20563682A patent/JPS5994821A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6384141A (en) * | 1986-09-29 | 1988-04-14 | Matsushita Electronics Corp | Manufacture of semiconductor device |
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