JPS59171115A - Manufacture of substrate for semiconductor device - Google Patents

Manufacture of substrate for semiconductor device

Info

Publication number
JPS59171115A
JPS59171115A JP4435883A JP4435883A JPS59171115A JP S59171115 A JPS59171115 A JP S59171115A JP 4435883 A JP4435883 A JP 4435883A JP 4435883 A JP4435883 A JP 4435883A JP S59171115 A JPS59171115 A JP S59171115A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
substrate
gaas
approximately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4435883A
Other languages
Japanese (ja)
Inventor
Katsuzo Uenishi
上西　勝三
Toshimasa Ishida
俊正 石田
Masahiro Akiyama
秋山　正博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4435883A priority Critical patent/JPS59171115A/en
Publication of JPS59171115A publication Critical patent/JPS59171115A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To use only small amount of special materials and obtain low cost compound semiconductor device by a method wherein at least one layer among Ge and GaAlAs is formed on a (100) Si substrate and a GaAs layer is deposited on it. CONSTITUTION:A Ge layer 2 with a thickness of approximately 1,000Angstrom -1mum is formed on a (100) plane Si substrate 1 with a thickness of approximately 150-500mum by electron beam deposition method or ion beam deposition method. If the orientation is not good enough at this stage, it is improved by heat-treatment in the H2 atmosphere at about 700 deg.C. Then a GaAs layer 3 is deposited on the layer 2 in the same way. Thus, the lattice constant difference of approximately 4% and the thermal expansion coefficient difference of 2.2 times between Si and GaAs are relieved by the Ge layer 2 so that the fitness between the GaAs layer 3 and the base is improved and an excellent active layer can be obtained. Although the Ge layer 2 is inserted in this explanation, a laminated layer of the Ge layer 2 and a GaAlAs layer 4 may be inserted.

Description

【発明の詳細な説明】 （技術分野） この発明は半導体装置基板、詳しくは化合物半碑体装を
斤基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device substrate, and more particularly to a method for manufacturing a semiconductor device substrate.

（従来技術） 従来の化合物半碑体装Ｒ：ｓ；板は、ガリウム砒素の結
晶を引き上は法なとで製作した後、それを３００μｍ〜
５００μｍの厚さにスライスし、さらにそのスライスし
た而を穴部ケＬＪＩしてイ乍っていた。(Prior art) Conventional compound half-mount R:s; The plate is made by pulling a gallium arsenide crystal using a method, and then cutting it to a thickness of 300 μm to 300 μm.
It was sliced to a thickness of 500 μm, and the sliced material was then cut into holes.

しかるに、このような方法では、スライシングするのに
その削り代として５０μｍ〜１００μｍ必要であり、ま
たその加工歪を除去し、表面を半導体装置基板として仕
上げるためにはさらに研摩を１０〜３０μｍ程度する必
要があり、したがって、特殊な材料を有効にオリ用する
点から考えると、極めて損失の多い作り方であった。However, with this method, a cutting allowance of 50 to 100 μm is required for slicing, and further polishing of about 10 to 30 μm is required to remove processing distortion and finish the surface as a semiconductor device substrate. Therefore, from the point of view of effective use of special materials, this was an extremely costly method of manufacturing.

（発明の目的） この発明は上記の点に鑑みなされたもので、特殊な材料
が少量ですみ安価に化合物半導体装置基版金製造できる
半導体装置基板の製造方法を提供することを目的とする
。(Objective of the Invention) The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device substrate, which requires a small amount of special materials and can manufacture a compound semiconductor device substrate at low cost.

（実施例） 以下この発明の実施例全図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to all the drawings.

第１図はこの発明の第１の実施例により製造された半導
体装置基板を示すＩＧｆ面図である。この第１図を参照
してこの発明の第１の実施例を１ず説明する。第１図に
おいて、１は厚み１５０μｍ〜５００μｍの（１００）
面シリコン単結晶基敬であり、まず、この基板１上に電
子ビーム蒸看法またはイオンビーム蒸ＡＡ法に上りり゛
ルマニウム層２ｖｘｏｏｏＡ〜１μｍ程度形成する。こ
こで、ケ゛ルマニウム層２を形成したままでは配向性が
充分でない場合は、次に、たとえば７００℃程度の水素
雰囲気中で熱処理することにより、配向性を大幅に改善
する。そして、このようにしてケ゛ルマニウム層２を作
った後、気相成長法でガリウム砒素層を形成することに
より、（１００）面のガリウム砒素層３を前記ケ゛ルマ
ニウム層２上に得る。FIG. 1 is an IGf plane view showing a semiconductor device substrate manufactured according to a first embodiment of the present invention. A first embodiment of the present invention will be described first with reference to FIG. In Figure 1, 1 is (100) with a thickness of 150 μm to 500 μm.
First, an armanium layer is formed on the substrate 1 by electron beam evaporation or ion beam AA method to a thickness of about 2vxoooA to 1 .mu.m. Here, if the orientation is not sufficient with the kermanium layer 2 formed as it is, then the orientation is significantly improved by heat treatment in a hydrogen atmosphere at about 700° C., for example. After forming the kelmanium layer 2 in this manner, a gallium arsenide layer 3 having a (100) plane is obtained on the kelmanium layer 2 by forming a gallium arsenide layer by vapor phase growth.

ところで、シリコン結晶とガリウム砒素結晶では格子定
数で約４％、熱膨張係数で２．２倍と材料定数に差があ
るが、ケ゛ルマニウム結晶とガ“リウム砒累結晶とでは
格子定数で０．１２％、熱＃張係数で１２％と極めて拐
科定叙が近い鉋となる。したがって、シリコン単結晶基
板１上にケ゛ルマニウム層２を介在してガリウム砒素層
３を形成する上記第１の実施例によ−ｈば、表向のガリ
ウム砒素層３とＴ地とのなじみがよく、良好な能動層を
ガリウム砒素層３で形成できる。したがって、上記第１
の実施１タリにより製造された半導体装置基板（は、化
合物半導体装置の基板として有効に１史うことかでさる
。By the way, there is a difference in material constant between a silicon crystal and a gallium arsenide crystal, with a lattice constant of about 4% and a thermal expansion coefficient of 2.2 times, but a kermanium crystal and a gallium arsenide crystal have a lattice constant of 0.12. %, and the thermal tensile coefficient is 12%, which is very close to the standard.Therefore, in the first embodiment, a gallium arsenide layer 3 is formed on a silicon single crystal substrate 1 with a kermanium layer 2 interposed therebetween. Accordingly, the surface gallium arsenide layer 3 and the T base have good compatibility, and a good active layer can be formed from the gallium arsenide layer 3.
A semiconductor device substrate manufactured by the first embodiment of the present invention has been effectively used as a substrate for a compound semiconductor device.

そして、上記の第１の実施例によれば、特殊な材料の部
分全エピタキシャル成長で得ているので、その部分の素
材の使用量が少なくてすみ安１曲に化合物半導体装置基
板ｆ：得ることができる。さらに、一般にシリコン基板
に比較して化合物半導体の基板はもろくて半導体装置製
造プロセス中でのハンドリング性が悪く、割れる問題が
多く発生するが、上記実施例によれば、シリコン基板上
に化合物半導体能動層を形成する方法であるから、この
問題も解決できる。According to the first embodiment, the compound semiconductor device substrate f is obtained by partial and total epitaxial growth of a special material. can. Furthermore, compound semiconductor substrates are generally more brittle than silicon substrates, making them difficult to handle during the semiconductor device manufacturing process, and causing many problems with cracking. Since this is a method of forming layers, this problem can also be solved.

なお、第１の実施例では、シリコン単結晶基板１上にｒ
ルマニウム層２を形成したが、とのケ゛ルマニウム層に
代えて、気相成長によりガリウノ、アルミニウム砒素層
を形成することによっても同様の効果を得ることができ
る。Note that in the first embodiment, r
Although the rumanium layer 2 was formed, the same effect can be obtained by forming a gallium or aluminum arsenide layer by vapor phase growth instead of the rumanium layer.

第２図はこの発明の第２の実施例により製造された半導
体装置基板の断面図である。この第２図に示すように、
この発明の第２の実施例では、（１００）面シリコン単
結晶基板ｌの上にグ゛ルマニウム層２を形成し、さらに
ガリウムアルミニウム砒素層４を形成し／こ上に、１ｊ
ｈ動層となる力゛リウム砒索ノー３を形成する。FIG. 2 is a sectional view of a semiconductor device substrate manufactured according to a second embodiment of the present invention. As shown in this Figure 2,
In a second embodiment of the present invention, a gallmanium layer 2 is formed on a (100) plane silicon single crystal substrate l, and a gallium aluminum arsenide layer 4 is formed on top of the gallium aluminum arsenide layer 4.
A force argon cord No. 3 is formed which becomes a dynamic layer.

このような第２の実施例によれば、第１の実施例と同一
の効果のほかに、ガリウム砒素層３の厚みが薄くても良
好な能動層を形成できる効果がある。すなわち、シリコ
ン、ケ゛ルマニウムは■族であり、力゛リウム砒索に対
してドーパントとなるが、間にガリウムアルミニウム砒
素層・１が入っていハ。According to the second embodiment, in addition to the same effects as the first embodiment, a good active layer can be formed even if the gallium arsenide layer 3 is thin. That is, silicon and kermanium belong to the group (1) and serve as dopants for the gallium arsenide, but there is a gallium aluminum arsenide layer 1 between them.

ば、これが、ｗｔ　ＱＪｊ層となるガリウム砒素層３の
キャリア督度力（犬きくなるのを防ぐ１動き−Ｃｆシ、
したがって、ガリウム砒素層３の）Ｌｙみが１隻くても
良好な１］シ動層を形１戎できろ。For example, this is the carrier concentration force of the gallium arsenide layer 3 which becomes the wt QJj layer (one movement to prevent it from becoming stiff - Cf),
Therefore, even if the gallium arsenide layer 3 has only one layer, it is possible to form a good 1) shear layer.

なお、このような第２の実７Ｉ伍１り１」において、各
層の詳細な製造方法は第１の実施例と同様である。In addition, in such a second embodiment, the detailed manufacturing method of each layer is the same as that of the first embodiment.

（う６明の効果） 以上詳述しにようにこの発明の製造方法ｊ−：おいで（
ｄ、シリコン皐結晶基４ノシ上に化合物半導体であるが
リウＪ“％　ｔｌｌ　：に層を形成するようにし１′ヒ
ので、特グ；（な刷科が少量１．でずみ女仙〕に化合物
半導体装置基板を製造することができ、しかも割れにく
い取扱い容易な化合物半導体装置基板を製造することが
できる。(Effect of U6 light) As detailed above, the manufacturing method of the present invention J-: Come (
d, although it is a compound semiconductor, it forms a layer on the silicon crystal base 4. A compound semiconductor device substrate can be manufactured, and a compound semiconductor device substrate that is difficult to break and easy to handle can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の半導体装置基板の製造方法の第１の
実施例を説明するための′断面図、第２図はこの発明の
第２の実施例を説明するだめの１υ１面図である。 １・・・（１００）面シリコン単結晶基板、２・・ケ゛
ルマニウム、；〆１．３・・ガリウム砒素層、４・・・
ガリウムアルミニウム砒素層。 特１−出願人　沖眠気工業株式会社FIG. 1 is a sectional view for explaining a first embodiment of the method for manufacturing a semiconductor device substrate of the present invention, and FIG. 2 is a 1υ plane view for explaining the second embodiment of the present invention. . 1...(100) plane silicon single crystal substrate, 2...Kalmanium; 1.3...Gallium arsenide layer, 4...
Gallium aluminum arsenide layer. Special Feature 1 - Applicant Okinemiki Kogyo Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] （ｉｏｏ）而のシリコン単結晶基板上に、ケ゛ルマニウ
ム層とガリウムアルミニウム砒素層のうち少なくとも一
層を形成し、その層上にガリウム砒素層を形成すること
を特徴とする＃導体装置基板の製造方法。(ioo) #A method for manufacturing a conductor device substrate, comprising forming at least one of a kermanium layer and a gallium aluminum arsenide layer on the silicon single crystal substrate, and forming a gallium arsenide layer on the layer.
JP4435883A 1983-03-18 1983-03-18 Manufacture of substrate for semiconductor device Pending JPS59171115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4435883A JPS59171115A (en) 1983-03-18 1983-03-18 Manufacture of substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4435883A JPS59171115A (en) 1983-03-18 1983-03-18 Manufacture of substrate for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59171115A true JPS59171115A (en) 1984-09-27

Family

ID=12689284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4435883A Pending JPS59171115A (en) 1983-03-18 1983-03-18 Manufacture of substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59171115A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842217A1 (en) * 2002-07-12 2004-01-16 St Microelectronics Sa GROWTH OF A MONOCRYSTALLINE REGION OF A III-V COMPOUND ON A MONOCRYSTALLINE SILICON SUBSTRATE
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842217A1 (en) * 2002-07-12 2004-01-16 St Microelectronics Sa GROWTH OF A MONOCRYSTALLINE REGION OF A III-V COMPOUND ON A MONOCRYSTALLINE SILICON SUBSTRATE
EP1427000A1 (en) * 2002-07-12 2004-06-09 STMicroelectronics S.A. Growth of a single crystal region of a III-V compound on a single crystal silicon substrate
US7033438B2 (en) 2002-07-12 2006-04-25 Stmicroelectronics S.A. Growth of a single-crystal region of a III-V compound on a single-crystal silicon substrate
US8686472B2 (en) 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

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