JPH01243513A - Compound semiconductor substrate - Google Patents
Compound semiconductor substrateInfo
- Publication number
- JPH01243513A JPH01243513A JP6949788A JP6949788A JPH01243513A JP H01243513 A JPH01243513 A JP H01243513A JP 6949788 A JP6949788 A JP 6949788A JP 6949788 A JP6949788 A JP 6949788A JP H01243513 A JPH01243513 A JP H01243513A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- lattice
- substrate
- intermediate layer
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 150000001875 compounds Chemical class 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 9
- 229910017384 Fe3Si Inorganic materials 0.000 abstract description 8
- 229910012990 NiSi2 Inorganic materials 0.000 abstract 3
- 238000000313 electron-beam-induced deposition Methods 0.000 abstract 2
- 229910018999 CoSi2 Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 42
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 101100282111 Caenorhabditis elegans gap-2 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000003362 semiconductor superlattice Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＳｉ基板上にＧａＡｓ等の■−Ｖ族化合物半導
体層を形成することにより得られる化合物半導体基板に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor substrate obtained by forming a -V group compound semiconductor layer such as GaAs on a Si substrate.
ＧａＡｓ等の化合物半導体は、高い電子移動度と直接遷
移型のバンド構造を持っているために、高速デバイス、
発光デバイス等に利用されている。Compound semiconductors such as GaAs have high electron mobility and a direct transition type band structure, so they are suitable for high-speed devices,
Used in light-emitting devices, etc.
また、ＧａＡｓ等の化合物半導体の薄膜結晶の成長が活
発に研究され、それらを使ったデバイスが試作されてい
る。これらのデバイスの実現化のために、低価格で大規
模面積基板等の利点を持つ、Ｓｉ基板を利用することが
期待されている。そこで、Ｓｉ基板上へＧ ａ Ａ ｓ
単結晶層を形成することが望まれているが、ＧａＡｓは
Ｓｉよりも格子定数が大きく、直接Ｓｉ基板上に良質の
単結晶層を成長させることができない。そのため、Ｓｉ
基板とＧ ａ Ａ ｓ層の間に格子の不整合を解消する
ための何らかの中間層が必要である。Furthermore, the growth of thin film crystals of compound semiconductors such as GaAs is being actively researched, and devices using them are being prototyped. In order to realize these devices, it is expected to use a Si substrate, which has advantages such as low cost and large area substrate. Therefore, Ga As is applied onto the Si substrate.
Although it is desired to form a single crystal layer, GaAs has a larger lattice constant than Si, and it is not possible to grow a high quality single crystal layer directly on a Si substrate. Therefore, Si
Some intermediate layer is required between the substrate and the GaAs layer to overcome the lattice mismatch.
従来のＳｉ基板上にＧａＡｓ層を形成した化合物半導体
基板には、中間層としてＧｅ層や５ｉ１−ＸＧｅＸ層、
または、他の二元、三元の化合物半導体層を利用する方
法等があり、中でも超格子を用いて格子の不整合を解消
することが行われていた。例えば、第２図に示す、特開
昭６２−５８６１６号公報として開示されているように
、中間層２０として格子定数の少しずつ異なるＧａＰ２
１゜Ｇ ａ Ａ ｓ ｏ、５Ｐｏ＊３等の化合物半導体
による超格子層２２．２３を積み重ねることによって、
約４％異なるＳｉからＧ ａ Ａ ｓの格子定数の不整
合を解消していた。なお、３０はＧａＡｓ成長層。A conventional compound semiconductor substrate in which a GaAs layer is formed on a Si substrate has a Ge layer, a 5i1-XGeX layer, or a 5i1-XGeX layer as an intermediate layer.
Alternatively, there are methods using other binary or ternary compound semiconductor layers, among which a superlattice has been used to eliminate lattice mismatch. For example, as shown in FIG. 2 and disclosed in Japanese Unexamined Patent Publication No. 62-58616, GaP2 with slightly different lattice constants is used as the intermediate layer 20.
By stacking superlattice layers 22 and 23 made of compound semiconductors such as 1°G a So, 5Po*3,
The mismatch between the lattice constants of Si and GaAs, which differ by about 4%, was resolved. Note that 30 is a GaAs growth layer.
ＧａＡｓ等の化合物半導体薄膜デバイスでは、その基板
に熱的安定性が要求される。従来の化合物半導体の超格
子層を用いた中間層では、熱的安定性に欠け、超格子層
形成後、高温処理を加えることができない。Compound semiconductor thin film devices such as GaAs require thermal stability in their substrates. An intermediate layer using a conventional compound semiconductor superlattice layer lacks thermal stability and cannot be subjected to high-temperature treatment after the superlattice layer is formed.
本発明の目的は、一般に熱的に安定であるシリサイドを
中間層としで用い、高温処理に耐え得る中間層を形成し
た上で、Ｓｉ基板とＧａＡｓ層の間の約４％の格子の不
整合を解決することにある。The purpose of the present invention is to use silicide, which is generally thermally stable, as an intermediate layer to form an intermediate layer that can withstand high-temperature processing, and to reduce the lattice mismatch of approximately 4% between the Si substrate and the GaAs layer. The goal is to solve the problem.
一般に、ＧａＡｓ層にデバイスを形成する場合、不純物
の拡散工程や層間絶縁膜を形成する工程で。Generally, when forming a device in a GaAs layer, this is done in the process of diffusing impurities or forming an interlayer insulating film.
基板の温度を上昇させる必要がある。そのため、Ｓｉと
ＧａＡｓ層の中間層に超格子を用いた基板では上述の工
程中に超格子構造が破壊され、Ｓｉ基板表面からＧａＡ
ｓ層に向かう転移の伝搬が抑制できなくなり、良好な結
晶性をもつＧａＡｓ層を維持できなくなる。そこで各種
デバイスを形成するための熱処理工程に耐え得る超格子
構造が必要とされていた。It is necessary to raise the temperature of the substrate. Therefore, in a substrate using a superlattice in the intermediate layer between Si and GaAs, the superlattice structure is destroyed during the above process, and the GaAs is removed from the surface of the Si substrate.
The propagation of dislocation toward the s-layer cannot be suppressed, and a GaAs layer with good crystallinity cannot be maintained. Therefore, there was a need for a superlattice structure that could withstand the heat treatment process used to form various devices.
上記目的は、Ｓｉ基板とＧａＡｓ層の間に中間層として
、Ｓｉ（格子定数５．４３人）と格子整合するＮ１５ｉ
ｚ（格子定数５．４１人）、あるいは、Ｃｏ５１２（格
子定数５．３８人）と、Ｇ ａ Ａ ｓ（格子定数５．
６５人）と格子整合するＦｅ３Ｓｉ（格子定数５．６６
人）を用いることにより、耐熱性の高い超格子構造を形
成することができ、デバイス形成過程における熱処理を
経てもＧ ａ Ａ ｓ層の初期の結晶性を維持すること
ができる。The above purpose is to use N15 as an intermediate layer between the Si substrate and the GaAs layer, which is lattice-matched to Si (lattice constant 5.43).
z (lattice constant 5.41 people), or Co512 (lattice constant 5.38 people) and G a A s (lattice constant 5.38 people).
Fe3Si (lattice constant 5.66), which is lattice-matched with
By using a superlattice structure with high heat resistance, the initial crystallinity of the GaAs layer can be maintained even after heat treatment in the device formation process.
Ｓｉ基板と格子整合するＮ１５ｉｚやＣｏ Ｓ ｉ ｚ
と、ＧａＡｓ層と格子整合するＦｅ３Ｓｉの超格子構造
を形成することにより、格子定数の不整合による転位の
伝搬をおさえ、熱的に安定な結晶性シリサイド中間層を
もち、高温処理に耐える化合物半導体基板が得られる。N15iz and Co Si z that lattice match with Si substrate
By forming a Fe3Si superlattice structure that lattice-matches with the GaAs layer, it suppresses the propagation of dislocations due to lattice constant mismatch, has a thermally stable crystalline silicide intermediate layer, and is a compound semiconductor that can withstand high-temperature processing. A substrate is obtained.
以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
Ｓｉ基板１上に中間層２として電子ビーム蒸着法により
Ｎ１５ｉｚ層２１を１００Å以上形成する。A N15iz layer 21 with a thickness of 100 Å or more is formed as an intermediate layer 2 on a Si substrate 1 by electron beam evaporation.
成長温度は６００−７００℃で、ＭＢＥ成長させる。次
に、Ｎ ｉ Ｓ ｉ ｘ層２１の上に、第二の中間層２
２としてＮ ｉ Ｓ ｉ ｚとＦｅ３Ｓｉの超格子層を
数１０人の厚さで中層積層する。これにより、約４％の
格子の不整合を解消する。この超格子層２２の上に第三
の中間層２ａとして、Ｆｅ３Ｓｉ層を電子ビーム蒸着法
により、１００Å以上形成した後、ＭＢＥ法により、Ｇ
ａＡｓ層３を成長温度６００℃、成長速度１μｍ／ｈで
０．５ μｍ形成し、最終的に単結晶ＧａＡｓ層を得る
。The growth temperature is 600-700°C, and MBE growth is performed. Next, on the N i S i x layer 21, a second intermediate layer 2 is formed.
2, superlattice layers of N i S i z and Fe3Si are laminated to a thickness of several tens of layers. This eliminates about 4% of the lattice mismatch. After forming a Fe3Si layer of 100 Å or more as the third intermediate layer 2a on this superlattice layer 22 by electron beam evaporation, G
An aAs layer 3 of 0.5 μm is formed at a growth temperature of 600° C. and a growth rate of 1 μm/h to finally obtain a single crystal GaAs layer.
本発明によれば、欠陥が少なく、良質、低価格で、高温
処理に耐えることができ、熱的に安定な化合物半導体基
板が得られる。According to the present invention, it is possible to obtain a thermally stable compound semiconductor substrate that has few defects, is of good quality, is inexpensive, can withstand high-temperature processing, and is thermally stable.
第１図は本発明の一実施例の断面図、第２図は従来例の
断面図である。
１・・・Ｓｉ基板、２・・・シリサイド中間層、２１・
・・Ｎ１５ｉｚ、２ｚ−Ｎ ｉ Ｓ ｉｚ／ Ｆ ｅａ
ｓ ｉのＳＬＳ、２ａ＝・Ｆｅ３Ｓｉ、３−ＧａＡｓ成
長層。
第１図
第２図FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Silicide intermediate layer, 21.
・・N15iz, 2z-N i S iz/ F ea
SLS of s i, 2a = .Fe3Si, 3-GaAs growth layer. Figure 1 Figure 2
Claims (1)
ｏＳｉ＿２あるいはＮｉＳｉ＿２からなり前記Ｓｉ基板
に接して形成された第一の中間層と、前記第一の中間層
を形成するＣｏＳｉ＿２あるいはＮｉＳｉ＿２とＦｅ＿
３Ｓｉとの超格子構造からなり、前記第一の中間層上に
形成された第三の中間層と、Ｆｅ＿３Ｓｉからなり、前
記第二の中間層上に形成された第三の中間層の三層を構
成することを特徴とする化合物半導体基板。 ２、特許請求の範囲第１項において、 前記第二の中間層として前記ＣｏＳｉ＿２あるいはＮｉ
Ｓｉ＿２を一方の層とし、前記Ｆｅ＿３Ｓｉと前記Ｃｏ
Ｓｉ＿２あるいは前記ＮｉＳｉ＿２との混晶を他方の層
とする超格子構造を用いたことを特徴とする化合物半導
体基板。[Claims] 1. C between the Si substrate and the III-V compound semiconductor layer
A first intermediate layer made of oSi_2 or NiSi_2 and formed in contact with the Si substrate, and CoSi_2 or NiSi_2 and Fe_2 forming the first intermediate layer.
A third intermediate layer consisting of a superlattice structure with 3Si and formed on the first intermediate layer, and a third intermediate layer consisting of Fe_3Si and formed on the second intermediate layer. A compound semiconductor substrate comprising: 2. In claim 1, the CoSi_2 or Ni is used as the second intermediate layer.
With Si_2 as one layer, the Fe_3Si and the Co
A compound semiconductor substrate characterized by using a superlattice structure in which the other layer is Si_2 or a mixed crystal with NiSi_2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6949788A JPH01243513A (en) | 1988-03-25 | 1988-03-25 | Compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6949788A JPH01243513A (en) | 1988-03-25 | 1988-03-25 | Compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01243513A true JPH01243513A (en) | 1989-09-28 |
Family
ID=13404414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6949788A Pending JPH01243513A (en) | 1988-03-25 | 1988-03-25 | Compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01243513A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463254A (en) * | 1992-10-30 | 1995-10-31 | International Business Machines Corporation | Formation of 3-dimensional silicon silicide structures |
| WO1995033285A1 (en) * | 1994-05-31 | 1995-12-07 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Silicon thin film on glass substrate |
-
1988
- 1988-03-25 JP JP6949788A patent/JPH01243513A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5463254A (en) * | 1992-10-30 | 1995-10-31 | International Business Machines Corporation | Formation of 3-dimensional silicon silicide structures |
| WO1995033285A1 (en) * | 1994-05-31 | 1995-12-07 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Silicon thin film on glass substrate |
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