JPS6222477A - Base-grounded semiconductor device - Google Patents
Base-grounded semiconductor deviceInfo
- Publication number
- JPS6222477A JPS6222477A JP16220685A JP16220685A JPS6222477A JP S6222477 A JPS6222477 A JP S6222477A JP 16220685 A JP16220685 A JP 16220685A JP 16220685 A JP16220685 A JP 16220685A JP S6222477 A JPS6222477 A JP S6222477A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- emitter
- base
- bonding pad
- pad electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はベース接地型半導体装置に関し、特に高周波用
に使用されるベース接地型バイポーラトランジスタのチ
ップの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a common base type semiconductor device, and particularly to the structure of a chip of a common base type bipolar transistor used for high frequencies.
従来、この種のバイポーラトランジスタのエミッタ電極
とベース電極はチップの同一平面上に形成されており、
しかも電気的短絡を防ぐ為にも平面的にある必要なる距
離を取って配置されるのが一般的である。この構造の場
合は、エミッタ電極パッドとコレクタ領域との間にある
量の浮遊容量が存在する。しかもその浮遊容量はベース
接地の場合、動作を不安定にした′り周波数帯域を狭く
する。Conventionally, the emitter and base electrodes of this type of bipolar transistor are formed on the same plane of the chip.
Furthermore, in order to prevent electrical short circuits, they are generally arranged at a certain distance from each other in a plane. With this structure, there is some amount of stray capacitance between the emitter electrode pad and the collector region. Moreover, when the base is grounded, the stray capacitance makes the operation unstable and narrows the frequency band.
特に高周波分野で使用されるトランジスタにおいては、
その動作周波数において、できるだけ大きい利得が要求
されるだけでなく異常発振が起きにくいという動作の安
定性が重要である。また広帯域高出力用においては、高
出力だけでなく、動作周波数帯域が広く効率が良い事も
強く要求され □ることになる。Especially in transistors used in high frequency fields,
At that operating frequency, not only is a gain as large as possible required, but also operational stability is important, such that abnormal oscillations are unlikely to occur. In addition, for broadband high output applications, there is a strong demand for not only high output but also a wide operating frequency band and good efficiency.
その為にはトランジスタチップの帰還容量を小 □
さくする事が必須であり、ベース接地型トランジスタの
場合は、具体的にはエミッタコレクタ浮遊容量を低減す
ることである。ところが従来技術では、上記浮遊容量を
小さくする有力な手段としてエミッタポンディグバット
の面積をできるたく小さくしたり、エミッタポンディン
グパッド、直下の絶縁膜の厚さを厚くしたりする手段が
講じられている。For this purpose, reduce the feedback capacitance of the transistor chip □
In the case of a common base type transistor, specifically, it is necessary to reduce the emitter-collector stray capacitance. However, in the prior art, effective means for reducing the above-mentioned stray capacitance include reducing the area of the emitter bonding pad as much as possible and increasing the thickness of the emitter bonding pad and the insulating film directly below it. There is.
しかしながらこれらの手段は逆にボンディング作業を難
しくしたり、チップの微細パターンの形成を困難にする
。またエミッタコレクタ浮遊容量の低減にも、従来技術
では限度がある。However, these methods conversely make bonding work difficult and make it difficult to form fine patterns of chips. There is also a limit to the reduction of emitter-collector stray capacitance with conventional techniques.
本発明は上記した従来の欠点を除去し、エミッタボンデ
ィング電極パッドとコレクタ領域との間の浮遊容量を基
本的には零に近くし、高周波トランジスタのＲＦ動作を
安定にし、高帯域化及び高効率化したベース接地型半導
体装置を提供することを目的とする。The present invention eliminates the above-mentioned conventional drawbacks, makes the stray capacitance between the emitter bonding electrode pad and the collector region basically close to zero, stabilizes the RF operation of high frequency transistors, and achieves high bandwidth and high efficiency. The purpose of the present invention is to provide a grounded base type semiconductor device.
本発明のベース接地型半導体装置はエミッタベース及び
コレクタの３つの領域からなり、かつ外部への電極取り
出しの為の金属化されたエミッタ電極、ベース電極及び
コレクタ電極の３つの電極領域からなる半導体チップを
有するベース接地型半導体装置において、エミッタポン
ディングパッド電極部の直下に、ある厚さのシリコン酸
化膜またはシリコン窒化膜等の絶縁膜を介して、エミッ
タポンディングパッド電極部とほぼ同じ面積を有するベ
ース電極と電気的に接続されたメタライズ領域を配置し
た構造、を有して構成される。即ち上記の手段を講する
と、従来技術ではどんなことをしても零に近くまで低減
できなかったエミッタポンディングパッド部とコレクタ
領域との間のコレクタエミッタ間浮遊容量（ＭＯＳ容量
）を零に近くまで低減することができる。The base-grounded semiconductor device of the present invention is a semiconductor chip consisting of three regions: an emitter base and a collector, and three electrode regions: a metalized emitter electrode, a base electrode, and a collector electrode for taking out the electrodes to the outside. In a common base type semiconductor device having an emitter bonding pad electrode section, an insulating film such as a silicon oxide film or a silicon nitride film of a certain thickness is placed directly under the emitter bonding pad electrode section, and the emitter bonding pad electrode section has approximately the same area as the emitter bonding pad electrode section. The structure includes a metallized region electrically connected to a base electrode. In other words, by taking the above measures, the collector-emitter stray capacitance (MOS capacitance) between the emitter bonding pad and the collector region, which could not be reduced to near zero with the conventional technology, can be reduced to near zero. It can be reduced to
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の一実施例及びその製造
方法を説明するために工程順に示した平面図であり、第
１図（ｃ）が本発明の一実施例の平面図である。FIGS. 1(a) to 1(c) are plan views shown in the order of steps for explaining an embodiment of the present invention and its manufacturing method, and FIG. 1(c) is a plan view of an embodiment of the present invention. It is a diagram.
まず、第１図（ａ）に示すように、従来技術の拡散・酸
化及びリソグラフィ技術を駆使してトランジスタのエミ
ッタ、ベース及びコレクタ領域を形成する。次いでベー
ス電極１及びエミッタ電極２を形成する。この場合コレ
クタ電極は反対側の平面に形成する。First, as shown in FIG. 1(a), the emitter, base, and collector regions of a transistor are formed using conventional diffusion, oxidation, and lithography techniques. Next, a base electrode 1 and an emitter electrode 2 are formed. In this case, the collector electrode is formed on the opposite plane.
なお、この場合エミッタ電極２を取り囲むように形成し
、しかもベース電極１と電気的に接続された新たなメタ
ライズ領域３を形成する。しかもこのメタライズ領域３
はその後形成されるエミッタポンディングパッド電極７
とほぼ同じか少し大きい位に配置するのが好ましい。In this case, a new metallized region 3 is formed to surround the emitter electrode 2 and to be electrically connected to the base electrode 1. Moreover, this metallized area 3
is the emitter bonding pad electrode 7 to be formed afterwards.
It is preferable to place it at a location that is approximately the same as or slightly larger than .
次に、第１図（ｂ）に示すように、シリコン酸化膜又は
シリコン窒化膜等の絶縁膜をＣＶＤ法により全面に被覆
した後、リングラフィ技術によりベースポンディングパ
ッド電極４とエミッタ電極２の部分に、それぞれ絶縁膜
上に開孔された窓５゜６を形成する。これによりベース
ボンディングバッド用電極が露出する。Next, as shown in FIG. 1(b), after coating the entire surface with an insulating film such as a silicon oxide film or a silicon nitride film using the CVD method, the base bonding pad electrode 4 and the emitter electrode 2 are formed using a phosphorography technique. Windows 5 and 6 are formed on the insulating film in the respective portions. This exposes the base bonding pad electrode.
次に、第１図（ｃ）に示すように、エミッタポンディン
グパッド電極を形成すれば本実施例のトランジスタチッ
プは完成する６
即ち本実施例は、エミッタ、ベース及びコレクタの３つ
の領域からなり、かつ外部への電極取り出しの為の金属
化されたエミッタ電極、ベース電極及びコレクタ電極の
３つの電極領域からなる半導体チップを有するベース接
地型半導体装置において、前記半導体チップのエミッタ
側ポンディングパッド電極部７の直下に絶縁膜を介して
ベース電極と同電位のメタライズ領域３が配置された構
造として得られる。Next, as shown in FIG. 1(c), the transistor chip of this embodiment is completed by forming an emitter bonding pad electrode.6 In other words, this embodiment consists of three regions: an emitter, a base, and a collector. , and a base-grounded semiconductor device having a semiconductor chip consisting of three electrode regions: a metalized emitter electrode, a base electrode, and a collector electrode for taking out the electrode to the outside, the emitter-side bonding pad electrode of the semiconductor chip A structure is obtained in which the metallized region 3 having the same potential as the base electrode is placed directly under the portion 7 with an insulating film interposed therebetween.
第２図（ａ）、（ｂ）は本発明の詳細な説明するための
本実施例と従来例のエミッタボンディングパ・ソド部の
電気的等価回路図であり第２図（ａ）が本実施例、第２
図（ｂ）が従来例のものである。すなわち、従来例では
エミッタ、コレクタ間の浮遊容量はＣＣＥで表わせるが
本実施例ではベースを介してエミッタ、ベース間の浮遊
容量ＣＥＢとベース、コレクタ間の浮遊容量ＣａＣが直
列に接続されたことになり、ベース接地型トランジスタ
の性能を下げる原因となるコレクタエミッタ浮遊容量（
ＭＯ３容量）を零に近くすることが可能となる。FIGS. 2(a) and 2(b) are electrical equivalent circuit diagrams of the emitter bonding path/sod part of the present embodiment and the conventional example for explaining the present invention in detail, and FIG. Example, 2nd
Figure (b) shows a conventional example. That is, in the conventional example, the stray capacitance between the emitter and the collector can be expressed as CCE, but in this embodiment, the stray capacitance CEB between the emitter and the base and the stray capacitance CaC between the base and the collector are connected in series through the base. collector-emitter stray capacitance (
MO3 capacity) can be made close to zero.
以上説明したように本発明のベース接地型■・ランジス
タにおいて、エミッタボンディッグバッド電極直下にも
、絶縁膜を介してベース電極と同一電位を保つメタライ
ズ領域を設けることにより、従来構造では不可避のエミ
ッタポンディングパッド電極とコレクタ領域との間のＭ
Ｏ３容量を、基本的には零に近くすることができ、高周
波トランジスタのＲＦ動作を安定にし広帯域化及び高効
率化等に大きな効果がある。As explained above, in the base-grounded transistor of the present invention, by providing a metallized region directly under the emitter bonding pad electrode that maintains the same potential as the base electrode through an insulating film, it is possible to M between the bonding pad electrode and the collector region
Basically, the O3 capacitance can be made close to zero, which has a great effect on stabilizing the RF operation of high frequency transistors, widening the band and increasing efficiency.
第１図（＆）〜（ｃ）は本発明の一実施例及びその製造
方法を説明するために工程順に示した断面図、第２図（
ａ） 、（ｂ）は本発明の一実施例の効果を説明するた
めの本実施例及び従来例のエミッタポンディングパッド
部の電気的等価回路図である。
１・・・ベース電極、２・・・エミッタ電極、３・・・
ベース電８ｉ！１と同電位のメタライズ領域、４・・・
ベースポンディングパッド電極、５・・・ベースボンデ
ィングバッド用窓、６・・・エミッタ電極用窓、７・・
・エミッタポンディングパッド電極、Ｅ・・・エミッタ
、Ｂ・・・ベース、Ｃ・・・コレクタ、ＣＩ！Ｂ・・・
エミッタ・ベースＭＯ３容量、ＣＲ２・・・ベース・コ
レクタＭＯ３容量、ＣＣＩ！・・・コレクタ・エミッタ
ＭＯ３容量。
率２ ＠Figures 1 (&) to (c) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention and its manufacturing method, and Figure 2 (
1A and 2B are electrical equivalent circuit diagrams of emitter bonding pad portions of this embodiment and a conventional example for explaining the effects of an embodiment of the present invention. 1...Base electrode, 2...Emitter electrode, 3...
Base electric 8i! 1 and the metallized region with the same potential, 4...
Base bonding pad electrode, 5... Window for base bonding pad, 6... Window for emitter electrode, 7...
・Emitter bonding pad electrode, E...emitter, B...base, C...collector, CI! B...
Emitter/base MO3 capacitance, CR2...base/collector MO3 capacitance, CCI! ...Collector-emitter MO3 capacitance. Rate 2 @
Claims (1)
かつ外部への電極取り出しの為の金属化されたエミッタ
電極、ベース電極及びコレクタ電極の３つの電極領域か
らなる半導体チップを有するベース接地型半導体装置に
おいて、前記半導体チップのエミッタ側ボンディング用
パッド電極部の直下に絶縁膜を介して、ベース電極の１
部が配置されていることを特徴とするベース接地型半導
体装置。Consists of three areas: emitter, base and collector.
In a base-grounded semiconductor device having a semiconductor chip consisting of three electrode regions, a metalized emitter electrode, a base electrode, and a collector electrode for taking out an electrode to the outside, a pad electrode portion for bonding on the emitter side of the semiconductor chip. 1 of the base electrode via an insulating film directly under the
A common base type semiconductor device characterized in that a base-grounded semiconductor device is arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16220685A JPS6222477A (en) | 1985-07-22 | 1985-07-22 | Base-grounded semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16220685A JPS6222477A (en) | 1985-07-22 | 1985-07-22 | Base-grounded semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6222477A true JPS6222477A (en) | 1987-01-30 |
Family
ID=15749988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16220685A Pending JPS6222477A (en) | 1985-07-22 | 1985-07-22 | Base-grounded semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6222477A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0225035A (en) * | 1988-07-13 | 1990-01-26 | Rohm Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4530332Y1 (en) * | 1967-06-19 | 1970-11-20 |
-
1985
- 1985-07-22 JP JP16220685A patent/JPS6222477A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4530332Y1 (en) * | 1967-06-19 | 1970-11-20 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0225035A (en) * | 1988-07-13 | 1990-01-26 | Rohm Co Ltd | Semiconductor device |
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