JPS6222470B2 - - Google Patents

Info

Publication number
JPS6222470B2
JPS6222470B2 JP53158584A JP15858478A JPS6222470B2 JP S6222470 B2 JPS6222470 B2 JP S6222470B2 JP 53158584 A JP53158584 A JP 53158584A JP 15858478 A JP15858478 A JP 15858478A JP S6222470 B2 JPS6222470 B2 JP S6222470B2
Authority
JP
Japan
Prior art keywords
layer
insulating layer
sio
glass layer
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53158584A
Other languages
Japanese (ja)
Other versions
JPS5586165A (en
Inventor
Michitaka Shimazoe
Yukio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15858478A priority Critical patent/JPS5586165A/en
Publication of JPS5586165A publication Critical patent/JPS5586165A/en
Publication of JPS6222470B2 publication Critical patent/JPS6222470B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Pressure Sensors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は、繰り返しひずみを与えても電気特性
の劣化がない信頼度の高い半導体ひずみ変換器の
製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a highly reliable semiconductor strain transducer whose electrical characteristics do not deteriorate even when subjected to repeated strain.

半導体ひずみ変換器は、例えば第1図に示す如
く、周辺部に肉厚部12、中央部に肉薄部13を
有する凹型のn型シリコン基板1よりなるシリコ
ン素子を固定台11に接着してなり、圧力が加わ
ると肉薄部13がたわみダイアフラムとして作動
する構造となつており、n型シリコン基板1の肉
薄部13の片面には不純物(ポロン)を拡散した
p型のゲージ抵抗領域(以下p型ゲージ抵抗と称
する)2が拡散処理により形成され、圧力pによ
り生じた肉薄部13のひずみをp型ゲージ抵抗2
の抵抗変化として検出するように構成されてい
る。
For example, as shown in FIG. 1, the semiconductor strain transducer is made by bonding a silicon element made of a concave n-type silicon substrate 1 having a thick part 12 at the periphery and a thin part 13 at the center to a fixed base 11. The structure is such that when pressure is applied, the thin wall portion 13 bends and operates as a diaphragm, and one side of the thin wall portion 13 of the n-type silicon substrate 1 is provided with a p-type gauge resistance region (hereinafter referred to as a p-type gauge resistance region) in which impurities (poron) are diffused. A p-type gauge resistor 2 (referred to as a gauge resistor) 2 is formed by a diffusion process, and the strain in the thin part 13 caused by the pressure p is absorbed by the p-type gauge resistor 2.
It is configured to detect as a change in resistance.

このp型ゲージ抵抗をn型シリコン基板1の一
部に形成するには、通常、プレーナ法と称する二
酸化シリコン(SiO2)層をマスクとする選択拡散
プロセスが用いられ、このような方法で作成され
たシリコン素子は第2図の如き構造となる。
To form this p-type gauge resistor in a part of the n-type silicon substrate 1, a selective diffusion process using a silicon dioxide (SiO 2 ) layer as a mask, called the planar method, is normally used. The resulting silicon device has a structure as shown in FIG.

図において、3は下部SiO2層、4はリンガラ
ス層、5は上部SiO2層、6はアルミニウム電極
である。
In the figure, 3 is a lower SiO 2 layer, 4 is a phosphor glass layer, 5 is an upper SiO 2 layer, and 6 is an aluminum electrode.

ここで下部SiO2層3膜は選択拡散の際のマス
クとして使用したものであり、この下部SiO2
3上に設けられているリンガラス層4は、下部
SiO2層3中のナトリウムイオン等による正の固
定電荷量(一般にNFB/cm2と称する)を減少さ
せ、p型ゲージ抵抗2とn型シリコン基板1との
間のpn接合による絶縁を良好にするためのもの
で、リンガラス層4上の上部SiO2層5は気相反
応法(CVD法)により形成され、耐湿性の悪い
リンガラス層4を外部から保護するために形成し
たものである。
Here, the lower SiO 2 layer 3 film was used as a mask during selective diffusion, and the phosphor glass layer 4 provided on this lower SiO 2 layer 3
The amount of positive fixed charge (generally referred to as N FB /cm 2 ) due to sodium ions, etc. in the SiO 2 layer 3 is reduced, and the insulation by the pn junction between the p-type gauge resistor 2 and the n-type silicon substrate 1 is improved. The upper SiO 2 layer 5 on the phosphorus glass layer 4 is formed by a vapor phase reaction method (CVD method), and is formed to protect the phosphorus glass layer 4, which has poor moisture resistance, from the outside. be.

このような構成を有するシリコン素子は、歪み
変換器として使用すると繰り返しひずみ印加によ
りアルミニウム電極が断線し、電気特性の測定が
不可能になる欠点を有する。
A silicon element having such a configuration has the disadvantage that when used as a strain transducer, the aluminum electrodes break due to repeated strain application, making it impossible to measure electrical characteristics.

第3図はこの種のシリコン素子のコンタクト部
近傍の断面図を示す。コンタクト窓をホトエツチ
法により形成する際、下部SiO2層3、リンガラ
ス層4、上部SiO2層5からなる多層構造膜は、
中間層であるリンガラス層4が上下部のSiO2
3,5よりエツチングされ易いため、リンガラス
層がサイドエツチされ、えぐられてしまう。
FIG. 3 shows a cross-sectional view of the vicinity of the contact portion of this type of silicon element. When forming the contact window by photo-etching, the multilayer structure film consisting of the lower SiO 2 layer 3, the phosphor glass layer 4, and the upper SiO 2 layer 5 is
Since the phosphor glass layer 4, which is an intermediate layer, is more easily etched than the upper and lower SiO 2 layers 3 and 5, the phosphor glass layer is side-etched and gouged.

この上に蒸着によりアルミニウム電極を形成す
ると、アルミニウム電極6と上記多層絶縁膜間に
空洞7ができ、この空洞を起点としてアルミニウ
ム電極の一部に亀裂8が発生する。このような状
態のシリコンひずみ変換器に繰り返し歪みをかけ
るとアルミニウム電極は完全に分裂し断線事故が
発生する。
When an aluminum electrode is formed on this by vapor deposition, a cavity 7 is formed between the aluminum electrode 6 and the multilayer insulating film, and a crack 8 is generated in a part of the aluminum electrode starting from this cavity. If a silicon strain transducer in such a state is repeatedly strained, the aluminum electrodes will completely split, resulting in a disconnection accident.

本発明の目的は、表面安定化効果の優れた多層
構造の絶縁膜を用い、かつアルミニウム等金続電
極の断線事故の発生しない半導体ひずみ変換器の
製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor strain transducer that uses a multilayered insulating film with an excellent surface stabilizing effect and that does not cause disconnection of metal electrodes such as aluminum.

このため本発明は、半導体基板の一主面にひず
み感応領域を一体的に形成し、前記半導体基板の
主面およびひずみ感応領域上に下部絶縁層、リン
ガラス層、及び上部絶縁層の3層からなる絶縁層
を形成し、前記ひずみ感応領域上の絶縁層に2個
の貫通孔を設け、この貫通孔に金属電極を設けた
半導体ひずみ変換器において、前記下部絶縁層と
リンガラス層の2層と、前記上部絶縁層には、異
なるエツチング工程によつて貫通孔を形成し、前
記上部絶縁層に形成される貫通孔を下部絶縁層に
形成される貫通孔より大きくなるようにしたもの
である。
Therefore, in the present invention, a strain sensitive region is integrally formed on one main surface of a semiconductor substrate, and three layers of a lower insulating layer, a phosphor glass layer, and an upper insulating layer are formed on the main surface of the semiconductor substrate and the strain sensitive region. In the semiconductor strain transducer, an insulating layer is formed, two through holes are provided in the insulating layer on the strain sensitive region, and metal electrodes are provided in the through holes. through-holes are formed in the upper insulating layer and the upper insulating layer by different etching processes, and the through-holes formed in the upper insulating layer are larger than the through-holes formed in the lower insulating layer. be.

以下、本発明の一実施例を図面に基づいて説明
する。
Hereinafter, one embodiment of the present invention will be described based on the drawings.

第4図は本発明になるシリコンひずみ変換器の
一実施例のコンタント部近傍の断面図である。1
はn型シリコン基板、2はp型ゲージ抵抗、3は
下部SiO2層、4はリンガラス層、5は上部SiO2
層、6はアルミニウム電極を示す。
FIG. 4 is a sectional view of the vicinity of a contact portion of an embodiment of the silicon strain transducer according to the present invention. 1
is an n-type silicon substrate, 2 is a p-type gauge resistor, 3 is a lower SiO 2 layer, 4 is a phosphorus glass layer, 5 is an upper SiO 2 layer
Layer 6 represents an aluminum electrode.

コンタクト用の絶縁膜の窓が上部で大きく、下
部で小さい二段構造となつていること、およびア
ルミニウム電極と絶縁膜間には空洞ができない特
徴がある。このため本発明になるシリコンひずみ
変換器はコンタクト部近傍でも空洞を起点とする
アルミニウム電極の亀裂は発生しなく、繰り返し
歪みを加えてもアルミニウム電極の断線事故はお
こらない。
It has a two-tiered structure in which the contact insulating film window is large at the top and small at the bottom, and there is no cavity between the aluminum electrode and the insulating film. Therefore, in the silicon strain transducer of the present invention, cracks in the aluminum electrode starting from the cavity do not occur even in the vicinity of the contact portion, and breakage of the aluminum electrode does not occur even when strain is repeatedly applied.

本構造のコンタクト用絶縁膜の窓は次の方法で
形成する。
The contact insulating film window of this structure is formed by the following method.

ゲージ抵抗2を有するn型シリコン基板1の表
面に下部SiO2層3およびリンガラス層4をつけ
ておく。その後ホトエツチ法によりリンガラス層
4と下部SiO2層3に60μmφの穴をあける。次
に気相反応法により上部SiO2層5を形成し、
1000℃で焼きしめる。この時、上記60μmφの穴
上の絶縁膜は上部SiO2層5だけがあり、それ以
外の部分の絶縁膜は下部SiO2層3、リンガラス
層4、上部SiO2層5の三層構造となつている。
またこの時リンガラス層の側面は上部SiO2層5
によつて覆われ、露出していない。
A lower SiO 2 layer 3 and a phosphor glass layer 4 are applied to the surface of an n-type silicon substrate 1 having a gauge resistor 2 . Thereafter, holes with a diameter of 60 μm are made in the phosphor glass layer 4 and the lower SiO 2 layer 3 by photo-etching. Next, an upper SiO 2 layer 5 is formed by a gas phase reaction method,
Bake at 1000℃. At this time, the insulating film above the 60 μmφ hole has only the upper SiO 2 layer 5, and the other parts of the insulating film have a three-layer structure of the lower SiO 2 layer 3, the phosphor glass layer 4, and the upper SiO 2 layer 5. It's summery.
Also, at this time, the side surface of the phosphorus glass layer is covered with the upper SiO 2 layer 5.
covered by and not exposed.

次に上記60μmφの上部SiO2層5の内側に50
μmφの窓をホトエツチ法により形成するが、リ
ンガラス層が表面にでていなくエツチ液に浸され
ないため、サイドエツチのないコンタクト用窓が
形成できる。
Next, 50 μm inside the upper SiO 2 layer 5 with a diameter of 60 μm
A window of μmφ is formed by photo-etching, but since the phosphor glass layer is not exposed to the surface and is not immersed in the etchant, a contact window without side etching can be formed.

このようにコンタクト用窓を二段ホトエツチ法
により形成するとアルミニウム電極形成後も空洞
は発生しない。
If the contact window is formed by the two-step photo-etching method in this manner, no cavities will be generated even after the aluminum electrode is formed.

第5図は本発明の他の実施例のコンタクト部近
傍の断面図を示す。
FIG. 5 shows a sectional view of the vicinity of the contact portion of another embodiment of the present invention.

第4図と比較し、リンガラス層4の側面が露出
している点が異なるが、コンタクト窓は外側で大
きく内側で小さくなり、アルミニウム電極との間
に空洞を発生していないことは共通である。
Compared to Fig. 4, the difference is that the side surface of the phosphor glass layer 4 is exposed, but the contact window is larger on the outside and smaller on the inside, and it is common that there is no cavity between it and the aluminum electrode. be.

本構造のコンタクト窓は三層の絶縁膜を形成し
た後、まず上部SiO2層5だけにホトエツチ法に
より大きな穴を形成し、次にリンガラス層4およ
び下部SiO2層3にホトエツチ法により小さな穴
を形成する。本方法は第4図の例に比較し、リン
ガラス層に直接レジストを塗る工程がないため、
リンガラス層の汚染がない特徴を持つ。
For the contact window of this structure, after forming a three-layer insulating film, first a large hole is formed only in the upper SiO 2 layer 5 by photo-etching, and then a small hole is formed in the phosphor glass layer 4 and the lower SiO 2 layer 3 by photo-etching. form a hole. Compared to the example shown in Figure 4, this method does not include the step of directly applying resist to the phosphorus glass layer.
It is characterized by no contamination of the phosphorus glass layer.

以上本発明によれば多層構造の絶縁膜特に中間
部にエツチング速度の速いリンガラス層を持つ多
層絶縁膜に対しても、コンタクト窓部でのリンガ
ラス層のえぐれはない。
As described above, according to the present invention, there is no gouging of the phosphor glass layer at the contact window portion even in a multilayer insulating film having a multilayer structure, particularly a multilayer insulating film having a phosphor glass layer with a high etching rate in the middle portion.

このため電極を形成しても空洞は発生しなく、
繰り返しひずみを加えても電極断線のおこらない
半導体ひずみ変換器を得ることができる。
For this reason, no cavities are generated even when electrodes are formed.
It is possible to obtain a semiconductor strain transducer in which electrode disconnection does not occur even when repeated strain is applied.

また望ましくは本発明においてコンタクト窓の
上部の大きさと下部の大きさの差を絶縁膜の厚さ
の2倍以上にすることである。かかる構造にする
ことによりコンタクト窓の平均傾斜は45゜以下と
なり金属電極のステツプカバリツジが良くなり、
より金属電極の断線が発生しにくい構造となる。
Further, in the present invention, it is preferable that the difference between the upper and lower portions of the contact window is at least twice the thickness of the insulating film. With this structure, the average slope of the contact window is less than 45 degrees, and the step coverage of the metal electrode is improved.
This results in a structure in which disconnection of the metal electrode is less likely to occur.

以上本実施例ではリンガラスを中間層とする
SiO2−リンガラス−SiO2の3層構造膜について
述べたが、リンガラスなどの絶縁膜上にそれより
エツチ速度の遅い絶縁膜を持つ場合、その絶縁膜
が如何なるものでも本発明が適用できることはあ
きらかである。
In this example, phosphorus glass is used as the intermediate layer.
Although the three-layer structure film of SiO 2 -phosphorus glass-SiO 2 has been described, the present invention can be applied to any type of insulating film when an insulating film with a slower etch rate is formed on an insulating film such as phosphorous glass. is obvious.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体ひずみ変換器の断面模式
図、第2図は従来の半導体素子の断面模式図、第
3図は従来の半導体素子のコンタクト近傍部の断
面図、第4図、第5図は本発明になる半導体ひず
み変換器用半導体素子のコンタクト近傍の断面図
である。 1……シリコン基板、2……ゲージ抵抗、3…
…下部SiO2層、4……リンガラス層、5……上
部SiO2層、6……アルミニウム電極。
Fig. 1 is a schematic cross-sectional view of a conventional semiconductor strain transducer, Fig. 2 is a schematic cross-sectional view of a conventional semiconductor element, Fig. 3 is a cross-sectional view of a conventional semiconductor element near a contact, Figs. The figure is a sectional view of a semiconductor element for a semiconductor strain transducer according to the present invention near a contact. 1...Silicon substrate, 2...Gauge resistance, 3...
...Bottom SiO 2 layer, 4...Phosphorous glass layer, 5...Upper SiO 2 layer, 6...Aluminum electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の一主面にひずみ感応領域を一体
的に形成し、前記半導体基板の主面およびひずみ
感応領域上に下部絶縁層、リンガラス層、及び上
部絶縁層の3層からなる絶縁層を形成し、前記ひ
ずみ感応領域上の絶縁層に2個の貫通孔を設け、
この貫通孔に金属電極を設けた半導体ひずみ変換
器において、前記下部絶縁層とリンガラス層の2
層と、前記上部絶縁層には、異なるエツチング工
程によつて貫通孔を形成し、前記上部絶縁層に形
成される貫通孔を下部絶縁層に形成される貫通孔
より大きくなるようにしたことを特徴とする半導
体ひずみ変換器の製造方法。
1. A strain sensitive region is integrally formed on one main surface of the semiconductor substrate, and an insulating layer consisting of three layers, a lower insulating layer, a phosphor glass layer, and an upper insulating layer, is formed on the main surface of the semiconductor substrate and the strain sensitive region. forming and providing two through holes in the insulating layer on the strain sensitive region,
In a semiconductor strain transducer in which a metal electrode is provided in the through hole, two of the lower insulating layer and the phosphor glass layer are provided.
through-holes are formed in the upper insulating layer and the upper insulating layer by different etching processes, and the through-holes formed in the upper insulating layer are larger than the through-holes formed in the lower insulating layer. A method for manufacturing a semiconductor strain transducer featuring features.
JP15858478A 1978-12-25 1978-12-25 Semiconductor strain transducer Granted JPS5586165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15858478A JPS5586165A (en) 1978-12-25 1978-12-25 Semiconductor strain transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15858478A JPS5586165A (en) 1978-12-25 1978-12-25 Semiconductor strain transducer

Publications (2)

Publication Number Publication Date
JPS5586165A JPS5586165A (en) 1980-06-28
JPS6222470B2 true JPS6222470B2 (en) 1987-05-18

Family

ID=15674875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15858478A Granted JPS5586165A (en) 1978-12-25 1978-12-25 Semiconductor strain transducer

Country Status (1)

Country Link
JP (1) JPS5586165A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117972A (en) * 1977-03-25 1978-10-14 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117972A (en) * 1977-03-25 1978-10-14 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS5586165A (en) 1980-06-28

Similar Documents

Publication Publication Date Title
CA1115857A (en) Semiconductor absolute pressure transducer assembly and method
KR950000096B1 (en) Formation of insulated contact aperture of semiconductor article
JPH0818068A (en) Manufacture of semiconductor distortion sensor
JPH063804B2 (en) Semiconductor device manufacturing method
JP2000058866A (en) Manufacture of small device
JPS6222470B2 (en)
JPS61222236A (en) Semiconductor device and manufacture thereof
JPH0330986B2 (en)
JPH0117248B2 (en)
JPS60130163A (en) Semiconductor ic
JPH0225037A (en) Silicon thin film transistor and its manufacture
JPS62155537A (en) Manufacture of semiconductor device
JP2808843B2 (en) Manufacturing method of semiconductor pressure sensor
JPH0573276B2 (en)
KR100264517B1 (en) Method for fabricating pressure sensor
JP3063165B2 (en) Semiconductor device and manufacturing method thereof
JPH0729711A (en) Forming method of resistor
JPH08274066A (en) Formation of contact window
JPH1140820A (en) Manufacture of semiconductor dynamic sensor
JP2570688B2 (en) Method for manufacturing semiconductor device
JPS6398156A (en) Manufacture of semiconductor pressure sensor
JPS61188948A (en) Manufacture of semiconductor device
JP4423789B2 (en) Manufacturing method of semiconductor capacitive sensor
JPH06120526A (en) Manufacture of semiconductor pressure sensor
JPH05166942A (en) Semiconductor device and manufacture thereof