JPS62214674A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristics of an FET by forming a recess, then coating a resist film pattern vertically from above with insulating film, further anisotropically etching it to allow the insulating film to remain on the sidewall of the recess, and coating the film vertically from above with a gate metal to suppress the expansion of the gate electrode. CONSTITUTION:An SiO2 film 16 is anisotropically etched by ion milling to remove by etching the film 16 coating the upper surfaces of a resist film pattern 14 and a recess 15 to allow the film 16 to remain n the sidewall of the recess. Then, a gate metal 17 made of aluminum is deposited from above to coat the upper surfaces of the pattern 14 and the recess 15 with the metal 17. Then, they are coated with the film 16, adn the film 16 is allowed to remain in the sidewall of the recess. Thus, even if the metal 17 is expanded laterally in the recess, it is separated by the film 15. therefore, a gate length becomes constant to reduce a parasitic capacity, thereby improving the characteristics of an FET.

Description

[Detailed Description of the Invention] [Summary] A spacer insulating film is deposited on a semiconductor substrate, a mask pattern is provided thereon, and the spacer insulating film is etched using the mask pattern as a shielding film to form a recessed portion. Form. Next, an insulating film is vertically deposited on the mask pattern and further anisotropically etched to leave the insulating film on the side walls of the recessed portion. Then, when gate metal is vertically deposited thereon, the spread of the gate metal is suppressed and the characteristics of the semiconductor device are improved.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a recess structure FET made of a compound semiconductor or the like.

For example, GaAs FE T (gallium arsenide field effect transistor) is known for use in satellite communications and terrestrial microwave communications;
A recess structure is created at T.

In FETs with this recessed structure, when a gate electrode is formed in the recessed part, the active layer under the gate electrode becomes thinner.
The FET has a structure in which a pinch-off operation is performed at high speed, and the cross-sectional area of the active layer is large under the source and drain electrodes, so the resistance can be reduced, and the high frequency operating characteristics are improved in this way. It is a structure.

Therefore, the formation of the gate electrode in the recessed portion is an important step, and the formation method must be thoroughly studied.

[Prior Art] Figures 2(a) to 2(e) show a conventional method of forming a recess portion and a gate electrode of a GaAsFET. , an n-type GaAs active layer 2 is epitaxially grown on a semi-insulating GaAs substrate 1, and AuGe (gold germanium) is grown on it.
After forming a source electrode S and a drain electrode consisting of
A 5i02 film (silicon oxide film) 3 having a thickness of 3000 to 4000 is deposited on the entire surface, and a resist film pattern 4 is further formed thereon. This resist film pattern 4 is a pattern in which windows are opened only in the recessed portions. Also, 5i0
The 2 film 3 is an insulating film for a spacer, and a silicon nitride film (Si3 N4 film) may be used in addition to the S+02 film.

Next, as shown in FIG. 2 (bl), using the resist film pattern 4 as a mask, the 5i02 film 3 is uniformly etched with a hydrofluoric acid solution to form a 5i0 film slightly wider than the window of the resist film.
A window of two membranes 3 is formed. Next, as shown in FIG.
If the As active N2 is 1000, the depth of the recess 5 is several hundred. Further, the etching depth is finely adjusted by passing a current through the active layer during etching and monitoring this current.

Next, as shown in FIG. 2 (di), a gate metal 6 made of aluminum is deposited from the top surface.

Then, as shown in the figure, the gate metal 6 is deposited on the resist film pattern 4, and the gate metal is deposited on the recessed portion 5 through the window of the resist film pattern 4, which becomes a gate electrode. Next, as shown in FIG. 4E, when the resist film pattern 4 is dissolved in an organic solvent and removed, the gate metal on the resist film pattern is lifted off and removed.

According to such a formation method, the recess portion 5 and the gate electrode are formed from the same window and are miniaturized.

In addition, the reason why the recessed portion 5 and gate electrode 6 are formed after first forming the source electrode S and the drain electrode as described above is that the formation of this recessed portion has a large influence on the characteristics of the FET. be.

[Problems to be Solved by the Invention] However, the above-mentioned formation method does not allow the 5i02 film 3 (spacer insulating film) to spread in the lateral direction and the gate metal 6
Spreading at the recess is unavoidable, and as a result, the gate metal adheres to or beyond the sidewalls of the recess, increasing the effective gate length and increasing parasitic capacitance. , there is a problem of deteriorating the characteristics of the FET.

The present invention proposes a method of forming FETs that solves these problems and improves the characteristics of FETs.

[Means for solving the problem] The purpose is to provide a mask pattern for forming a grooved portion on a semiconductor substrate via an insulating film for a spacer, and to etch the insulating film for a spacer using the mask pattern as a shielding film. Then, in the step of forming a recessed part, an insulating film is vertically deposited on the mask pattern, and the insulating film is anisotropically etched so that the insulating film remains on the side walls of the recessed part. This is achieved by a forming method that includes a step of vertically depositing gate metal on the mask pattern.

[In other words, the present invention etches the insulating film for a spacer using a conventional resist film pattern (mask pattern) as a mask to form a recessed part, and then etches the insulating film vertically from above the resist film pattern. The insulating film is deposited and further anisotropically etched to leave an insulating film on the side walls of the recessed portion, and a gate metal is vertically deposited thereon.

This suppresses the spread of the gate electrode (gate metal) and improves the characteristics of the FET.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 1 (al to hl) show step-by-step cross-sectional views of the formation method according to the present invention. First, as shown in FIG. 1 (81), an n-type GaAs active layer I
2 was epitaxially grown to form a source electrode S and a drain electrode made of AuGe.
A 5i02 film 13 (insulating film for a spacer) of ~4,000 layers is deposited over the entire surface, and a resist film pattern 14 is formed thereon, with windows opened only at the recess formation portions.

Next, as shown in FIG. 1 (bl), using the resist film pattern 14 as a mask, the 5i02 film 13 is etched in the same direction with a hydrofluoric acid solution to form windows in the 5i02 film 13. CCl2F, as shown in C).

The recess portion 15 is formed by anisotropic etching by RIE using gas. The depth of the depression is n-type GaA
If the number of active layers 12 is 1,000, the depth of the recessed portion 15 is about several hundred. The etching depth is monitored and adjusted by a monitor during etching.

The steps up to this point are similar to the conventional method.

Next, as shown in FIG. The 5i02 film 16 is then deposited.Then, as shown in the same figure (el), the 5i02 film 16 is deposited.
is anisotropically etched by ion milling to remove the StO□ film 16 deposited on the upper surface of the resist film pattern 14 and the surface of the recessed portion 15, leaving the 5i02 film 16 on the side walls of the recessed portion.

Next, as shown in FIG. 1(f), a gate metal 17 made of aluminum is deposited thereon to cover the upper surface of the resist film pattern 14 and the recessed portion 15 as shown in the figure.
Gate metal 17 is deposited on.

Next, as shown in FIG.
As shown in FIG. 1 (hl), the resist film pattern 14 is etched away by ion milling. Here, the steps described in FIG. This is a planarization method that fills the gap with the insulating film), and is not necessarily an essential step in the formation method according to the present invention.

Now, if the above-mentioned method of depositing 5io211i16 and leaving SiO2@16 on the side walls of the recessed area is adopted, even if the gate metal 17 spreads laterally in the recessed area, it will be isolated by the 5i02 film 16. Therefore, the gate length is constant, parasitic capacitance is reduced, and the characteristics of the FET can be improved.

[Effects of the Invention] As is clear from the description of the embodiments above, according to the present invention, the gate length of the FET having a recessed structure is regulated, and the FET
This greatly contributes to improving the characteristics of ET.

[Brief explanation of drawings]

FIG. 1 (al~(hl) is a step-by-step diagram of the formation method according to the present invention, 1.11 is a semi-insulating GaAs substrate, 2.12 is an n-type GaAs active layer, 3.13 is a 5i02 film (spar 4 m, in, 4.1
4 is a resist film pattern, 5.15 is a recessed portion, 6.17 is a 5i02 film as the gate metal 16, and 18 is an insulating organic resin. 4 invention); To the 3rd form 'To the young form °Tne \ Busan Shun mf
s 1 figure? BJ1+=1-#・SeJ'X'7;t/+y
n'Ine1pterynns@1 Figure

Claims (1)

[Claims] A step of providing a mask pattern for forming a recessed portion on a semiconductor substrate via an insulating film for a spacer, and etching the insulating film for a spacer using the mask pattern as a shielding film to form a recessed portion. Next, an insulating film is deposited vertically on the mask pattern, and the insulating film is anisotropically etched to leave the insulating film on the side walls of the recessed portion, and then the gate is deposited on the mask pattern. A method for manufacturing a semiconductor device, comprising a step of vertically depositing metal.