JPS62211990A - Structure of land for soldering parts - Google Patents
Structure of land for soldering partsInfo
- Publication number
- JPS62211990A JPS62211990A JP5360686A JP5360686A JPS62211990A JP S62211990 A JPS62211990 A JP S62211990A JP 5360686 A JP5360686 A JP 5360686A JP 5360686 A JP5360686 A JP 5360686A JP S62211990 A JPS62211990 A JP S62211990A
- Authority
- JP
- Japan
- Prior art keywords
- land
- conductor layer
- soldering
- dielectric
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title claims description 14
- 239000004020 conductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 10
- 239000010408 film Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 2
- 238000007790 scraping Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
厚膜混成集積回路における部品はんだ付用ランドの構造
であって、基板上に複数条の誘電体の突起を設け、その
上に導体層を形成することにより、導体層の膜厚が確保
され、信頼性のあるはんだ付けを可能とする。[Detailed Description of the Invention] [Summary] This is a structure of a land for soldering components in a thick film hybrid integrated circuit, in which a plurality of dielectric protrusions are provided on a substrate and a conductive layer is formed on the protrusions. , the film thickness of the conductor layer is ensured, and reliable soldering is possible.
本発明は厚膜混成集積回路における部品はんだ付用ラン
ドの改良に関するものである。The present invention relates to improvements in lands for soldering components in thick film hybrid integrated circuits.
従来、厚膜混成集積回路における部品はんだ付用ランド
は、基板(例えばアルミナ基板)上に厚膜ペーストを印
刷・乾燥し、然る後焼成することにより形成される。Conventionally, lands for soldering components in thick film hybrid integrated circuits are formed by printing and drying a thick film paste on a substrate (for example, an alumina substrate), and then baking it.
一般に厚膜におけるパターン幅と膜厚の関係は第3図に
示す通りであり、膜厚はパターン幅が略0.5調のとこ
ろに最大値があり、パターン幅が狭ければスクリーン印
刷時のインクの出が悪く、パターン幅が広いとインクが
スキージにかきとられてともに薄くなる。このため部品
はんだ付用ランドとして用いられる幅の広いパターンは
、配線パターンと同時に形成された場合には膜厚は薄く
なる。一方、はんだ何時のはんだと導体との拡散現象は
よく知られている現象であり、この拡散の進行により嗅
の密着強度は低下する。これらの理由から従来の部品は
んだ付用ランド、特にランド寸法の大きなものについて
はその膜厚が薄くなり接続信頼性が低くなるという欠点
があった。In general, the relationship between pattern width and film thickness for thick films is as shown in Figure 3. The film thickness has its maximum value when the pattern width is approximately 0.5 scale, and if the pattern width is narrow, If the ink does not flow well and the pattern width is wide, the ink will be scraped off by the squeegee and both will become thin. For this reason, a wide pattern used as a component soldering land will have a thin film thickness if it is formed simultaneously with a wiring pattern. On the other hand, the diffusion phenomenon between the solder and the conductor during soldering is a well-known phenomenon, and as this diffusion progresses, the strength of the adhesion decreases. For these reasons, conventional lands for soldering components, especially those with large land dimensions, have a drawback in that the film thickness is thin and the connection reliability is low.
本発明はこのような点Kfiみて創作されたもので、簡
易な構成で信頼性の高い部品はんだ付用ランドの構造を
提供することを目的としている。The present invention was created in view of these points Kfi, and an object of the present invention is to provide a structure of a component soldering land that has a simple configuration and high reliability.
このため本発明におりては、厚膜混成集積回路における
部品はんだ付用ランドの構造であって、上記基板1の上
に設けられた複数条の誘電体の突起2の上に導体層3が
形成されて成ることを特徴としている。Therefore, in the present invention, in the structure of a component soldering land in a thick film hybrid integrated circuit, a conductor layer 3 is formed on a plurality of dielectric protrusions 2 provided on the substrate 1. It is characterized by being formed.
スクリーン印刷時にスクリーンが誘電体の突起に保持さ
れるため、スキージ忙よるインクのかきと沙が防止され
導体層の膜厚の確保が可能となる。Since the screen is held by the protrusions of the dielectric during screen printing, ink scraping and smearing caused by the squeegee is prevented, and the thickness of the conductor layer can be ensured.
第1図は本発明の実施例を示す図である。同図において
1は基板、2は誘電体で形成された突起、3は導体であ
る。FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is a protrusion made of dielectric material, and 3 is a conductor.
本実施例は第1図に示すように、基板1の上のラン□ド
となる部分に複数条の誘電体の突起2を設けておき、そ
の上に導体層3を形成したものである0
このように構成された本実施例は誘電体の突起2の存在
により厚膜ペースト印刷時においてスクリーンが該突起
2により保持されるためスキージによるインクのかきと
りが少なくカリ、従って、あらゆる形状のランドにおい
ても導体層3の膜の厚さは確保される。このためはんだ
何時のはんだと導体の拡散による基板1と導体層3との
密着強度の低下は小さくなり部品のはんだ何部の接続信
頼性は増加する。In this embodiment, as shown in FIG. 1, a plurality of dielectric protrusions 2 are provided on a portion of a substrate 1 that will become a land, and a conductive layer 3 is formed on the protrusions 2. In this embodiment configured as described above, the presence of the dielectric projections 2 allows the screen to be held by the projections 2 during thick film paste printing, so there is less scraping of ink by the squeegee. Also, the thickness of the conductor layer 3 is ensured. Therefore, the reduction in adhesion strength between the substrate 1 and the conductor layer 3 due to the diffusion of the solder and the conductor during soldering is reduced, and the connection reliability of the soldered parts of the component is increased.
なお導体層3の誘電体突起2からの距離と膜厚との関係
は第2図に示す如くであり、距離jは0.5mm位まで
許容できるので突起2の間隔は1直根度以下がよい。The relationship between the distance from the dielectric protrusion 2 of the conductor layer 3 and the film thickness is as shown in Fig. 2. Since the distance j can be up to about 0.5 mm, the interval between the protrusions 2 should be 1 tap root degree or less. good.
以上述べてきたように、本発明によれば、極めて簡易な
構成で、厚膜混成集積回路圧おけるはんだ付用ランドの
導体層の膜厚を確保することができ、実用的には極めて
有用である。As described above, according to the present invention, it is possible to ensure the film thickness of the conductor layer of the soldering land in a thick film hybrid integrated circuit with an extremely simple configuration, and it is extremely useful in practice. be.
第1図は本発明の実施例を示す断面図、第2図は導体層
の誘電体突起からの距離と膜厚との関係を示す図、
第3図はパターン幅と導体層の膜厚との関係を示す図で
ある。
第1図において、
1は基板、
2は誘電体の突起、
3は導体層である。
本発明の実施例を示す図
第1図
1・・・基板
3・・・・導体層
誘電体から距離B(mm)
導体層の誘電体突起からの距離と
膜厚との関係を示す図FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the distance from the dielectric protrusion of the conductor layer and the film thickness, and FIG. 3 is a diagram showing the relationship between the pattern width and the film thickness of the conductor layer. FIG. In FIG. 1, 1 is a substrate, 2 is a dielectric projection, and 3 is a conductor layer. Figure 1 illustrating an embodiment of the present invention Figure 1: Substrate 3: Distance B (mm) from the conductor layer dielectric Figure showing the relationship between the distance from the dielectric protrusion of the conductor layer and the film thickness
Claims (1)
構造であって、 上記ランドは基板(1)の上に設けられた複数条の誘電
体の突起(2)の上に導体層(3)が形成されて成るこ
とを特徴とする部品はんだ付用ランドの構造。[Claims] 1. Structure of a land for soldering components in a thick film hybrid integrated circuit, wherein the land is formed on a plurality of dielectric protrusions (2) provided on a substrate (1). A structure of a land for soldering components, characterized in that a conductor layer (3) is formed on the land.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5360686A JPS62211990A (en) | 1986-03-13 | 1986-03-13 | Structure of land for soldering parts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5360686A JPS62211990A (en) | 1986-03-13 | 1986-03-13 | Structure of land for soldering parts |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62211990A true JPS62211990A (en) | 1987-09-17 |
Family
ID=12947547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5360686A Pending JPS62211990A (en) | 1986-03-13 | 1986-03-13 | Structure of land for soldering parts |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62211990A (en) |
-
1986
- 1986-03-13 JP JP5360686A patent/JPS62211990A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62211990A (en) | Structure of land for soldering parts | |
US5219607A (en) | Method of manufacturing printed circuit board | |
JPS63283051A (en) | Substrate for hybrid integrated circuit device | |
JPS62176191A (en) | Pads for soldering parts to thick film hybrid integrated circuit | |
JPS6141272Y2 (en) | ||
JPH0611531Y2 (en) | Circuit board device | |
JPS5849653Y2 (en) | printed wiring board | |
JP2603863B2 (en) | Printed wiring board | |
JPS61242095A (en) | Manufacture of printed wiring circuit board | |
JPS6251292A (en) | Manufacture of wiring circuit board | |
JPH1134473A (en) | Method for printing pattern | |
JPH05327196A (en) | Printed board for mounting electronic component using narrow pitch electrodes | |
JPH03297190A (en) | Printed wiring board | |
JPS5951589A (en) | Printed board | |
JPS6096868U (en) | printed wiring board | |
JPS60143688A (en) | Method of printing thick film circuit | |
JPS59141293A (en) | Multilayer circuit board | |
JPS62199091A (en) | Printed wiring board | |
JPS6354714A (en) | Manufacture of hybrid integrated circuit | |
JPS6263489A (en) | Printed board | |
JPS5851594A (en) | Thick film hybrid ic board | |
JPH0437191A (en) | Multi-layered printed board | |
JPS6010697A (en) | Method of producing multilayer circuit board | |
JPS583066U (en) | printed wiring board | |
JPS61100994A (en) | Manufacture of thick film circuit board |