JPS59141293A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPS59141293A JPS59141293A JP1657583A JP1657583A JPS59141293A JP S59141293 A JPS59141293 A JP S59141293A JP 1657583 A JP1657583 A JP 1657583A JP 1657583 A JP1657583 A JP 1657583A JP S59141293 A JPS59141293 A JP S59141293A
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- multilayer wiring
- window
- circuit board
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は多層配線基板の改良、特に微細化加工に適した
多層配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in multilayer wiring boards, particularly to multilayer wiring boards suitable for miniaturization.
(ロ)従来技術
従来の多層配線基板では第1図に示す多層配線を実現す
るには第2図の如(、セラミック等の絶縁基板(1)上
に銅箔等の第1の導電パターン(2)を形成し、その上
に絶縁材料を2度スクリーン印刷して十分に厚くした絶
縁物層(3)を設け、更にその上に第2の導電パターン
(4)を形成して構成していた。(B) Prior Art In a conventional multilayer wiring board, in order to realize the multilayer wiring shown in FIG. 2), an insulating material layer (3) made sufficiently thick by screen printing an insulating material twice is provided thereon, and a second conductive pattern (4) is further formed thereon. Ta.
頂上の構造では第1の導電パターン(2)と第2の導電
パターン(4)の接続部は絶縁材料のスクリーン印刷時
に選択的に窓(5)を形成して両者を接触できる様にし
ている。しかしながら絶縁材料は有機溶剤でペースト状
としてスクリーン印刷するので、窓(5)のエッヂが鮮
明に印刷できず第2図の如く内側ににじみが発生して窓
(5)がつぶされる危惧があった。このため窓(5)を
にじみを考慮して十分に大きく、例えば直径300μに
形成していた。この結果第1の導電パターン(2)およ
び第2の導電パターン(4)はこの大きさの窓(5)を
形成できるだけ十分に離間させる必要があり、微細化パ
ターン加工の障害となっていた。In the top structure, the connection between the first conductive pattern (2) and the second conductive pattern (4) is selectively formed with a window (5) during screen printing of the insulating material to allow contact between the two. . However, since the insulating material is screen printed in the form of a paste using an organic solvent, the edges of the window (5) could not be printed clearly, and as shown in Figure 2, there was a risk that bleeding would occur on the inside and the window (5) would be crushed. . For this reason, the window (5) is formed to be sufficiently large, for example, 300 μm in diameter, in consideration of bleeding. As a result, the first conductive pattern (2) and the second conductive pattern (4) had to be spaced apart from each other sufficiently to form a window (5) of this size, which was an obstacle to fine pattern processing.
(ハ) 目的
本発明は頂点に鑑みてなされ、従来の欠点を完全に除去
した極めて微細化加工に適した多層配線基板を提供する
ものである。(c) Purpose The present invention has been made in view of the top, and provides a multilayer wiring board suitable for extremely fine processing, completely eliminating the drawbacks of the conventional method.
に)構成
本発明に依れば、絶縁基板と、この上に形成された第1
の導電パターンと、絶縁材料により第1の導電パターン
を被覆する絶縁物層と、この上に形成された第2の導電
パターンとを具備し、接続部の第1の導電パターンを選
択的に厚く形成して構成される。B) Structure According to the present invention, an insulating substrate and a first
a conductive pattern, an insulating layer covering the first conductive pattern with an insulating material, and a second conductive pattern formed thereon, the first conductive pattern at the connection portion being selectively thickened. formed and composed.
(ホ)実施例
本発明は第3図に示す如く、セラミックあるいは表面を
酸化膜で被覆したアルミニウム等の絶縁基板(1)上に
第1の導電パターン(2)を形成する。第1の導電パタ
ーン(2)は絶縁基板(1)上に全面に銅箔を貼着した
後所望のパターンにエツチングして形成される。なお本
発明の最も特徴とする点であるが、接続点となる第1の
導電パターン(2)上には2〜50μ程度の突起(6)
を形成する。この突起(6)は選択的に無電界銅メッキ
あるいは電界ニッケルメッキによりメッキ層を付着して
形成するか、あるいは他の第1の導電パターン(2)を
ハーフエツチングして形成する。(e) Embodiment As shown in FIG. 3, in the present invention, a first conductive pattern (2) is formed on an insulating substrate (1) made of ceramic or aluminum whose surface is coated with an oxide film. The first conductive pattern (2) is formed by pasting copper foil over the entire surface of the insulating substrate (1) and then etching it into a desired pattern. The most distinctive feature of the present invention is that there is a protrusion (6) of approximately 2 to 50 μm on the first conductive pattern (2) that serves as the connection point.
form. The protrusion (6) is formed by selectively depositing a plating layer by electroless copper plating or electric field nickel plating, or by half-etching the other first conductive pattern (2).
次に第1の導電パターン(2)上を被覆する絶縁物層(
3) ヲスクリニン印刷する。絶縁材料としてはポリイ
ミドを用い、接続点に対応して形成される窓(5)を残
して基板(1)全面に2回刷りしてピーンホールの防止
と十分な膜厚の確保をしている。具体的には乾燥後30
〜40μ厚ぐらいになる様にスクリーン印刷する。この
透窓(5)の大きさは接続部の第1の導電パターン(2
)の突起(6)より若干大きい程度で良く、具体的には
直径200μを可能にできる。これはスクリーン印刷時
に窓(5)の内側ににじみが発生してもにじみは突起(
6)の端部で防止できるので、少くとも突起(6)上に
は絶縁物層(3)は印刷されない。Next, an insulating layer (
3) Print the screen immediately. Polyimide is used as the insulating material, and it is printed twice over the entire surface of the substrate (1), leaving windows (5) formed corresponding to the connection points, to prevent peen holes and ensure a sufficient film thickness. . Specifically, after drying 30
Screen print to a thickness of ~40μ. The size of this transparent window (5) is determined by the size of the first conductive pattern (2) of the connection part.
) may be slightly larger than the protrusion (6), and specifically, a diameter of 200μ can be achieved. This means that even if bleeding occurs inside the window (5) during screen printing, the bleeding will not occur on the protrusion (
6), the insulating layer (3) is not printed at least on the protrusion (6).
然る後絶縁物層(3)上に銀ペースト等の導電ペースト
のスクリーン印刷かあるいは無電界ニッケルメッキによ
り第2の導電パターン(4)を形成する。Thereafter, a second conductive pattern (4) is formed on the insulating layer (3) by screen printing a conductive paste such as silver paste or by electroless nickel plating.
この結果第2の導電パターン(4)は接続点で第1の導
電パターン(2)の突起(6)と確実に連結される。As a result, the second conductive pattern (4) is reliably connected to the protrusion (6) of the first conductive pattern (2) at the connection point.
(へ)効果
本発明に依れば第1の導電パターン(2)の突起(6)
により絶縁物層(3)の窓(5)を極めて高精度に形成
できるので、第1および第2の導電パターン(2)(4
)の間隔を小さくできる。これにより微細加工に適した
多層配線基板を実現でき、電子部品の高密度実装化が行
なえる。(f) Effect According to the present invention, the protrusion (6) of the first conductive pattern (2)
Since the window (5) of the insulator layer (3) can be formed with extremely high precision, the first and second conductive patterns (2) (4
) can be made smaller. As a result, a multilayer wiring board suitable for microfabrication can be realized, and electronic components can be mounted at high density.
第1図は一般的な多層配線基板を説明する上面板を説明
する第1図A−A線断面図である。
(1)は絶縁基板、(2)は第1の導電パターン、(3
)は絶縁物層、(5)は窓、(6)は突起、(4)は第
2の導電パターンである。
第1図FIG. 1 is a sectional view taken along the line A--A in FIG. 1 illustrating a top plate of a general multilayer wiring board. (1) is an insulating substrate, (2) is a first conductive pattern, (3
) is an insulating layer, (5) is a window, (6) is a protrusion, and (4) is a second conductive pattern. Figure 1
Claims (1)
導電パターンを被覆する絶縁物層と該絶縁物層上に設け
た第2の導電パターンを備え、前記第1の導電パターン
と第2の導電パターンの接続部の前記第1の導電パター
ンを厚く形成することを特徴とする多層配線基板。 2、特許請求の範囲第1項に於いて、前記接続部の第1
の導電パターン上に選択的にメッキ層を設けることを特
徴とする多層配線基板。[Claims] 1- A first conductive pattern provided on an insulating substrate, an insulating layer covering the first conductive pattern, and a second conductive pattern provided on the insulating layer, A multilayer wiring board, characterized in that the first conductive pattern at the connection portion between the first conductive pattern and the second conductive pattern is formed thick. 2. In claim 1, the first connecting portion
A multilayer wiring board characterized in that a plating layer is selectively provided on a conductive pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1657583A JPS59141293A (en) | 1983-02-02 | 1983-02-02 | Multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1657583A JPS59141293A (en) | 1983-02-02 | 1983-02-02 | Multilayer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59141293A true JPS59141293A (en) | 1984-08-13 |
Family
ID=11920084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1657583A Pending JPS59141293A (en) | 1983-02-02 | 1983-02-02 | Multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59141293A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9322468B2 (en) | 2011-06-24 | 2016-04-26 | Mitsubishi Electric Corporation | Reduction gear unit |
-
1983
- 1983-02-02 JP JP1657583A patent/JPS59141293A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9322468B2 (en) | 2011-06-24 | 2016-04-26 | Mitsubishi Electric Corporation | Reduction gear unit |
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