JPS62213195A - Formation of conductor pattern - Google Patents
Formation of conductor patternInfo
- Publication number
- JPS62213195A JPS62213195A JP5586786A JP5586786A JPS62213195A JP S62213195 A JPS62213195 A JP S62213195A JP 5586786 A JP5586786 A JP 5586786A JP 5586786 A JP5586786 A JP 5586786A JP S62213195 A JPS62213195 A JP S62213195A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- aluminum
- layer
- formation
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 title claims description 8
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
・〈産業上の利用分野〉
本発明は２例えば、ハイブリッドＩＣの導体パターン形
成の低コスト化および性能向上に関する。DETAILED DESCRIPTION OF THE INVENTION - <Industrial Application Field> The present invention relates to, for example, cost reduction and performance improvement in conductor pattern formation for hybrid ICs.
〈従来の技術〉
従来、ハイブリッドＩＣ等のセラミック基板への導体パ
ターンは銀等を含むペーストをシルクスクリーン印刷に
より形成している。<Prior Art> Conventionally, a conductor pattern on a ceramic substrate such as a hybrid IC is formed by silk screen printing with a paste containing silver or the like.
・〈発明が解決しようとする問題点〉
しかしながら、上記従来のシルクスクリーン印刷による
導体パターン形成法では次のような問題がある。-<Problems to be Solved by the Invention> However, the above-mentioned conventional conductor pattern forming method using silk screen printing has the following problems.
（１） ペーストに貴金属が含まれているので高価で
ある。(1) The paste contains precious metals, so it is expensive.
（２） スクリーンが０．３ｍｍ程度のメツシュであ
り、微細なパターン形成が困難である。(2) The screen is a mesh of about 0.3 mm, making it difficult to form fine patterns.
（３） 電気伝導度、熱伝達度が金属に比較して劣る
。(3) Electrical conductivity and heat transfer are inferior to metals.
本発明は上記問題点に鑑みて成されたもので。The present invention has been made in view of the above problems.
低コスト化、高信頼性化、高性能化および設計の自由度
の向上を図ることを目的とする。The aim is to reduce costs, increase reliability, improve performance, and improve design freedom.
く問題点を解決するための手段〉 上記問題点を解決するための本発明の構成は。Means to solve problems〉 The structure of the present invention for solving the above problems is as follows.
セラミック基板上にスパッタリングまたは蒸着によりア
ルミニウム層を形成し、前記アルミニウム層の上に銅層
を形成したことを特徴とするものである。It is characterized in that an aluminum layer is formed on a ceramic substrate by sputtering or vapor deposition, and a copper layer is formed on the aluminum layer.
〈実施例〉
一般にアルミニウムと銅の電気伝導度は同程度であり、
アルミニウムは銅に比較してハンダ付は性に劣るが、ア
ルミナ製のセラミック基板に対しては密着性がよい。本
発明は上記の特性を利用したものである。<Example> Generally, the electrical conductivity of aluminum and copper is about the same,
Aluminum has poor solderability compared to copper, but it has good adhesion to alumina ceramic substrates. The present invention takes advantage of the above characteristics.
図は本発明の導体パターン形成方法の一実施例を示す断
面図である。The figure is a sectional view showing an embodiment of the conductor pattern forming method of the present invention.
図において、１はハイブリッドＩＣ等のセラミック基板
であり、２は基板上に形成した例えば厚さ５μｍ程度の
アルミニウム層であり、３はアルミニウム層２の上に形
成した例えば厚さ０．１μｍ程度の銅層である。上記ア
ルミニウム１２およびｉ［３はスパッタリングまたは蒸
着により形成される。In the figure, 1 is a ceramic substrate such as a hybrid IC, 2 is an aluminum layer with a thickness of about 5 μm formed on the substrate, and 3 is a layer with a thickness of about 0.1 μm formed on the aluminum layer 2. It is a copper layer. The aluminum 12 and i[3 are formed by sputtering or vapor deposition.
上記構成によれば、アルミニウム１ｉＩ２を５μｍ程度
の下地層とし、ハンダ付は性に優れている銅層３を０．
１μｍ程度の厚さに形成しているので。According to the above structure, the base layer is made of aluminum 1iI2 with a thickness of about 5 μm, and the copper layer 3, which has excellent soldering properties, is made of aluminum 1iI2 with a thickness of about 5 μm.
It is formed to a thickness of about 1 μm.
セラミック基板に対する密着性が良くまたハンダ付は性
もよい。It has good adhesion to ceramic substrates and has good soldering properties.
なお、スパッタリングまたは蒸着された２つの金属のパ
ターン化は９例えば化学エツチングにより導体パターン
を形成してもよく、スパッタリング時にハードマスクを
併用し直接導体パターンを形成してもよい。For patterning the two sputtered or vapor-deposited metals, a conductor pattern may be formed by, for example, chemical etching, or a hard mask may be used during sputtering to directly form a conductor pattern.
また、アルミニウム層全体を覆って銅層を形成せず１部
品をハンダつけするラウンド部分のみに銅層を形成すれ
ば、セラミック基板およびアルミニウムの上にはハンダ
が付着しないので、ハンダディップによる部品実装が可
能となる。In addition, if you do not form a copper layer covering the entire aluminum layer, but instead form a copper layer only on the round part where one component is soldered, solder will not adhere to the ceramic board and aluminum, so component mounting by solder dip is possible. becomes possible.
〈発明の効果〉
以上、実施例とともに具体的に説明したように本発明に
よれば。<Effects of the Invention> According to the present invention, as described above in detail along with the embodiments.
（１） 貴金属を用いないので低コスト化が実現できる
。(1) Since no precious metals are used, costs can be reduced.
〈２） プリント基板の製造工程が利用できるの装置の
合理化をはかることができる。(2) It is possible to rationalize the equipment that can be used in the printed circuit board manufacturing process.
（３） シルクスクリーンを使用しないので微細なパタ
ーン形成が可能である。(3) Fine patterns can be formed because no silk screen is used.
（４） ペーストを使用しないので熱伝導が良好で放熱
設計が楽になり高密度化が可能になる。(4) Since no paste is used, heat conduction is good, making heat dissipation design easier and allowing for higher density.
（５） ソルダーレジスト不要のハンダディップが可能
になる。(5) Solder dip without the need for solder resist becomes possible.
等の効果がある。There are other effects.
図は本発明の一実施例を示す断面図である。
１・・・セラミック基板、２・・・アルミニウム層、３
・・・鋼層。The figure is a sectional view showing one embodiment of the present invention. 1... Ceramic substrate, 2... Aluminum layer, 3
...Steel layer.
Claims (1)
アルミニウム層を形成し、前記アルミニウム層の上に銅
層を形成したことを特徴とする導体パターン形成方法。A method for forming a conductor pattern, comprising forming an aluminum layer on a ceramic substrate by sputtering or vapor deposition, and forming a copper layer on the aluminum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5586786A JPS62213195A (en) | 1986-03-13 | 1986-03-13 | Formation of conductor pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5586786A JPS62213195A (en) | 1986-03-13 | 1986-03-13 | Formation of conductor pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62213195A true JPS62213195A (en) | 1987-09-19 |
Family
ID=13011025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5586786A Pending JPS62213195A (en) | 1986-03-13 | 1986-03-13 | Formation of conductor pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62213195A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03126540A (en) * | 1989-10-05 | 1991-05-29 | Internatl Business Mach Corp <Ibm> | Method for airtight-sealing defect in porous ceramic substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200755A (en) * | 1983-04-22 | 1984-11-14 | ホワイト・エンジニアリング・コ−パレイシヤン | Ion plating process |
| JPS61256688A (en) * | 1985-05-09 | 1986-11-14 | 松下電器産業株式会社 | Manufacture of circuit board |
-
1986
- 1986-03-13 JP JP5586786A patent/JPS62213195A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200755A (en) * | 1983-04-22 | 1984-11-14 | ホワイト・エンジニアリング・コ−パレイシヤン | Ion plating process |
| JPS61256688A (en) * | 1985-05-09 | 1986-11-14 | 松下電器産業株式会社 | Manufacture of circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03126540A (en) * | 1989-10-05 | 1991-05-29 | Internatl Business Mach Corp <Ibm> | Method for airtight-sealing defect in porous ceramic substrate |
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