JPS62209834A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JPS62209834A
JPS62209834A JP61051437A JP5143786A JPS62209834A JP S62209834 A JPS62209834 A JP S62209834A JP 61051437 A JP61051437 A JP 61051437A JP 5143786 A JP5143786 A JP 5143786A JP S62209834 A JPS62209834 A JP S62209834A
Authority
JP
Japan
Prior art keywords
insulating plate
plate
metal plate
semiconductor element
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61051437A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0476500B2 (enExample
Inventor
Shinjiro Kojima
小島　伸次郎
Nobuyuki Mizunoya
水野谷　信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61051437A priority Critical patent/JPS62209834A/ja
Publication of JPS62209834A publication Critical patent/JPS62209834A/ja
Publication of JPH0476500B2 publication Critical patent/JPH0476500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped

Landscapes

  • Die Bonding (AREA)
  • Wire Bonding (AREA)
JP61051437A 1986-03-11 1986-03-11 半導体装置及びその製造方法 Granted JPS62209834A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61051437A JPS62209834A (ja) 1986-03-11 1986-03-11 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61051437A JPS62209834A (ja) 1986-03-11 1986-03-11 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPS62209834A true JPS62209834A (ja) 1987-09-16
JPH0476500B2 JPH0476500B2 (enExample) 1992-12-03

Family

ID=12886906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61051437A Granted JPS62209834A (ja) 1986-03-11 1986-03-11 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JPS62209834A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110986A (ja) * 2000-09-28 2002-04-12 Fuji Electric Co Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110986A (ja) * 2000-09-28 2002-04-12 Fuji Electric Co Ltd 半導体装置

Also Published As

Publication number Publication date
JPH0476500B2 (enExample) 1992-12-03

Similar Documents

Publication Publication Date Title
KR900008665B1 (ko) 반도체장치의 제조방법
US4751199A (en) Process of forming a compliant lead frame for array-type semiconductor packages
US4774635A (en) Semiconductor package with high density I/O lead connection
US6917107B2 (en) Board-on-chip packages
JP2929273B2 (ja) ボールグリッドアレイ半導体パッケージ用ユニットｐｃｂキャリヤフレーム及びこれを用いるボールグリッドアレイ半導体パッケージの製造方法
CN102132403B (zh) 模制超薄半导体管芯封装和使用该封装的系统及其制造方法
US4865193A (en) Tape carrier for tape automated bonding process and a method of producing the same
EP0500750A1 (en) METHOD FOR HOUSING AN ELECTRONIC DEVICE ADHESIVE BY ADHESIVE TAPE AND HOUSING USED.
US5296737A (en) Semiconductor device with a plurality of face to face chips
USRE37416E1 (en) Method for manufacturing a modular semiconductor power device
JP2003124262A5 (enExample)
JPH0418694B2 (enExample)
EP0723293B1 (en) Semiconductor device with a heat sink and method of producing the heat sink
EP0474224B1 (en) Semiconductor device comprising a plurality of semiconductor chips
JPH0476500B2 (enExample)
EP0146463B1 (en) Compliant lead frame for surface mount semiconductor packages
JPS62104058A (ja) 半導体装置
JPH03228339A (ja) ボンディングツール
KR100250145B1 (ko) 비지에이반도체패키지와그제조방법
JPS61270850A (ja) 半導体チツプ実装用パツケ−ジ
JPS61272956A (ja) ハイブリツド型半導体装置
JPH03116765A (ja) リードフレーム
JPH05259365A (ja) 半導体用リード部材およびこれを用いた半導体装置
JPH0744190B2 (ja) パワ−ｉｃ装置の製造方法
JP2001024138A (ja) 複合リードフレーム

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term