JPS622089U - - Google Patents
Info
- Publication number
- JPS622089U JPS622089U JP9335485U JP9335485U JPS622089U JP S622089 U JPS622089 U JP S622089U JP 9335485 U JP9335485 U JP 9335485U JP 9335485 U JP9335485 U JP 9335485U JP S622089 U JPS622089 U JP S622089U
- Authority
- JP
- Japan
- Prior art keywords
- circuit means
- output
- generate
- video data
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図はこの考案のＣＲＴデイスプレイ装置の
ビデオ信号制御装置の一実施例を示す機能ブロツ
ク図、第２図は第１図に示したこの考案のＣＲＴ
デイスプレイ装置のビデオ信号制御装置の動作を
説明するためのタイムチヤートである。
図面において、１は時間監視回路で、１１はそ
の時間監視素子、１２はチヤージコンデンサ、１
３はトランジスタ、２はビデオ信号制御回路で、
２１はその遅延回路素子、２２はアンドゲート回
路素子、２３はオアゲート回路素子、２４はナン
ドゲート回路素子、３はビデオ信号出力回路で、
３１はそのフリツプフロツプ回路、４はインバー
タを示す。 FIG. 1 is a functional block diagram showing an embodiment of a video signal control device for a CRT display device of this invention, and FIG. 2 is a functional block diagram of a CRT display device of this invention shown in FIG.
3 is a time chart for explaining the operation of a video signal control device of a display device. In the drawing, 1 is a time monitoring circuit, 11 is a time monitoring element thereof, 12 is a charge capacitor, 1
3 is a transistor, 2 is a video signal control circuit,
21 is its delay circuit element, 22 is an AND gate circuit element, 23 is an OR gate circuit element, 24 is a NAND gate circuit element, 3 is a video signal output circuit,
31 is its flip-flop circuit, and 4 is an inverter.
Claims (1)
るスクリーンメモリと、キー入力の有無を監視し
、所定時間の経過により動作して出力信号を発生
する時間監視回路とを具備するＣＲＴデイスプレ
イ装置において、前記スクリーンメモリからのビ
デオデータ信号用のドツトクロツクを遅延させる
ための遅延回路手段と、該遅延回路手段の出力と
ドツトクロツクとをアンド処理して短いパルス幅
のクロツクを発生させるアンドゲート回路手段と
、該アンドゲート回路手段の出力とビデオデータ
信号との論理処理を行う論理回路手段とを設け、
前記時間監視回路が動作したとき、その出力信号
によつて、前記アンドゲート回路手段の出力と、
スクリーンメモリからのビデオデータ信号とのア
ンド処理を行うことにより、短いパルス幅のビデ
オ出力信号が発生されるように制御することを特
徴とするビデオ信号制御装置。 A CRT display device comprising a screen memory from which display data is read out in synchronization with raster scanning, and a time monitoring circuit that monitors the presence or absence of key input and operates to generate an output signal after a predetermined period of time has elapsed. delay circuit means for delaying a dot clock for a video data signal from the screen memory; AND gate circuit means for ANDing the output of the delay circuit means and the dot clock to generate a short pulse width clock; Logic circuit means for logically processing the output of the gate circuit means and the video data signal;
When the time monitoring circuit operates, its output signal causes the output of the AND gate circuit means to
1. A video signal control device that performs AND processing with a video data signal from a screen memory to generate a video output signal with a short pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9335485U JPS622089U (en) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9335485U JPS622089U (en) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS622089U true JPS622089U (en) | 1987-01-08 |
Family
ID=30650961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9335485U Pending JPS622089U (en) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS622089U (en) |
-
1985
- 1985-06-20 JP JP9335485U patent/JPS622089U/ja active Pending
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