JPS60109147U - Device that monitors abnormalities in arithmetic and control equipment - Google Patents
Device that monitors abnormalities in arithmetic and control equipmentInfo
- Publication number
- JPS60109147U JPS60109147U JP20291883U JP20291883U JPS60109147U JP S60109147 U JPS60109147 U JP S60109147U JP 20291883 U JP20291883 U JP 20291883U JP 20291883 U JP20291883 U JP 20291883U JP S60109147 U JPS60109147 U JP S60109147U
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic
- pulse signal
- control equipment
- output
- time interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は自動復帰手段を備えた従来の演算制御装置のブ
ロック図、第２図は本考案の一実施例を −示すブ
ロック図、第３図ａ ” ｅは第２図の装置の動作を説
明するためのタイムチャートである。
１・・・クロック発振器、２・・・演算制御装置、４゜
５・・・カウンタ、ＣＫ・・・クロックパルス、Ｐ□、
Ｐ２゜Ｐ３・・・パルス信号、）ＬＴ・・・停止信号。Fig. 1 is a block diagram of a conventional arithmetic and control device equipped with automatic return means, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 a `` e shows the operation of the device shown in Fig. 2. It is a time chart for explaining. 1... Clock oscillator, 2... Arithmetic control unit, 4° 5... Counter, CK... Clock pulse, P□,
P2゜P3...Pulse signal, )LT...Stop signal.
Claims (1)
演算制御装置から出力される第１のパルス信号を監視し
、そのパルス信号間隔が前記時間間隔を超えたとき第２
のパルス信号をイニシャライズ信号として前記演算制御
装置に送出する第１のタイマ一手段と、 前記第２のパルス信号が出力されてから前記時間間隔内
に前記第１のパルス信号が出力されなかったことをもっ
て故障と判断して停止信号を出力し、前記演算制御装置
を停止させる第２のタイマ、一手段と を備えてなる演算制御装置の異常を監視する接置。[Claims for Utility Model Registration] When a first pulse signal output from an arithmetic and control unit is monitored every time a predetermined program is executed at a certain time interval, and the pulse signal interval exceeds the time interval. Second
a first timer means for sending a pulse signal as an initialization signal to the arithmetic and control unit; and the first pulse signal is not output within the time interval after the second pulse signal is output. A second timer for determining a malfunction and outputting a stop signal to stop the arithmetic and control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20291883U JPS60109147U (en) | 1983-12-27 | 1983-12-27 | Device that monitors abnormalities in arithmetic and control equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20291883U JPS60109147U (en) | 1983-12-27 | 1983-12-27 | Device that monitors abnormalities in arithmetic and control equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60109147U true JPS60109147U (en) | 1985-07-24 |
Family
ID=30765342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20291883U Pending JPS60109147U (en) | 1983-12-27 | 1983-12-27 | Device that monitors abnormalities in arithmetic and control equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109147U (en) |
-
1983
- 1983-12-27 JP JP20291883U patent/JPS60109147U/en active Pending
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