JPS62204294A - Video signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In order to reduce the amount of data to be processed, image data is stored in discrete lines in the image memory, and when the image data is read out from the image memory and displayed on the display. The device is equipped with an address generation circuit that alternately performs a function of repeatedly generating the same address and a function of jumping the address by the amount of repetition, thereby interpolating and displaying discrete images.

[Industrial application field]

The present invention relates to a video signal generator.

When displaying digital image data supplied from a computer or stored in a disk device on a display (such as a CRT display), there is usually an image memory between the computer or disk device and the display. and a video signal generator, to which the present invention particularly refers.

[Conventional technology]

FIG. 7 is a block diagram showing the general configuration of a video display system. In this figure, the parts related to the present invention are a video signal generator (Video Sign
The image memory 14 is accessed by the address signal outputted through the address line L0, and the corresponding image data is read through the data line Lt11. This image data is subjected to predetermined processing to generate a video signal Sν, which is then used on a display.
) 16, the image (still image) is displayed on the display. Note that Lc is a control line when receiving control from the CPU 11.

A computer (CPU) 11 is stored in the image memory 14 in advance.
Or from disk device (Disk) 12 etc., bus 1
3, image data is supplied and stored. The address and image data at that time are the address line and the data line, respectively. The image data is applied to the image memory 14 via the . In this way, image data is stored in the image memory 14 in units of many pixels.

FIG. 8 is a diagram showing an example of an image stored in the image memory 14, and shows, for example, "A". However, an extremely large amount of data is required to represent this complete pattern "A". Therefore, for example, it takes a considerable amount of time to transfer the image data for "A" and other patterns from the disk device 12 to the image memory 14. Therefore, it is difficult to quickly switch the display on the display 16. This makes it difficult to respond, resulting in a sluggish display.

Therefore, "thinning" is generally performed. In other words, according to the above example, the image data is stored in the image memory 14, although the pattern is not a perfect "A", but the image data is displayed intermittently so that it can be read as "A" to some extent. 3 is a diagram showing an example of an image stored by thinning, in which image data is stored in the image memory 14 only at a ratio of one line for every n horizontal lines.As a result, the display quality on the display 16 is degraded, but the response is Fast image display is achieved.

[Problem that the invention seeks to solve]

Pattern 'A' shown in Fig. 9 clearly has inferior display quality.In other words, it cannot be said to be an easy-to-read pattern.'Various proposals have been made in the past to eliminate this drawback.The representative one is is what is called "interpolation." Interpolation means filling in the thinned out area by other means, and a well-known method is to fill in the image data of the line immediately before the thinned out line. There is a method of calculating the correlation between the line and the image data of the line immediately after it, and filling in the removed line with a more natural pattern.

Regardless of the well-known method mentioned above or any other method, in most cases interpolation is based on CPU processing, and the processing time is taken up to a certain extent, so it is difficult to see what is displayed on the display. There is a problem in that the response speed is not increased as much as a result.

[Means for solving problems]

The present invention is based on the premise that the above interpolation is performed entirely by hardware, thereby reducing the time required for interpolation processing. Also, for the interpolation method, a method that can be easily performed using hardware is adopted. Here, such hardware is implemented in an address generation circuit within a video signal generation device.

FIG. 1 is a diagram showing a schematic configuration of an address generation circuit according to the present invention. In this figure, as described above, 14 is an image memory, 15 is a video signal generator, and 16 is a display. The address generation circuit 20 in the video signal generation device 15 is a feature of the Zero invention. This address generation circuit 20 is, in principle, a jump address generation section (JM
P-AD) 21 and the cyclic address generator (C
YC-AD) 22, and the jump addresses and cyclic addresses from these generation parts are alternately ORed.
It is sent to the address line Lal via the gate. The image memory 14 is accessed using the address on this address line □, and the corresponding image data is read out and sent to the display 16 as a video signal Sv. LIN in this diagram
means a synchronization signal for each line.

[For production]

In FIG. 1, the jump address generation section 21 has 0 (
Every time scanning of lines (i is a natural number such as 2, 3.4, etc.) is completed (scanning on the display), an address for jumping to the address corresponding to the line where the next image data exists is generated. On the other hand, the cyclic address generating section 22 receives from the jump address generating section 21 the address corresponding to the line where the immediately preceding image data exists until reaching the line where the next image data exists. Output this cyclically. The addresses from the jump address generating section 21 and the cyclic address generating section 22 are alternately output to the image memory 14.

In short, conventional general address generation circuits only output addresses for access in order, that is, continuously, from the beginning to the end of the image memory 14, but the address generation circuit 20 of the present invention , the address can be output non-continuously. The key point of the present invention is that the address generation circuit itself automatically performs the interpolation function.

〔Example〕

FIG. 2 is a diagram showing an example of an image displayed according to the present invention, and similarly to the case described above, pattern "A" is shown. It is obvious at a glance that interpolation has been added to the image in Figure 9, and the pattern "A" is easier to see.
''.Now, focusing on the lines Lk and L+141, the image memory 14 has lines Lk and L+141.
Only image data corresponding to k+H is stored. Therefore, for the thinned out line L' group (2, 3 or 4 lines) up to the line Lk where the next image data exists, the address corresponding to the line Lk where the immediately previous image data exists. is repeatedly applied to the image memo IJ14, and these line L' groups are interpolated with the image data of line L. If expressed in black and white, a pattern with a high black pixel density and closer to the original image can be obtained. However, this interpolation method itself is publicly known.

FIG. 3 is a diagram showing an example of the overall configuration of the video signal generating device, in which the present invention is applied to the address generating circuit 20. In FIG. This circuit 20 is hardware that can be called an automatic interpolator, and is not controlled by the CPU 11 at all. IM and DSP in this figure are the image memory 14 and display 16 also shown in FIG. 1, etc.

The synchronization signal generation circuit 23 serves as the overall clock source, and generates and outputs vertical synchronization signals (V, yc), horizontal synchronization signals (Hsvc), and data strobe signals (Dirb) necessary for scanning on the display array 16. do. This data strobe signal (Dirb) serves as a timing signal for serially reading the image data buffered in the data register 25 and outputting it to the display DSP. On the other hand, the address generation circuit 20 uses these signals V□ゎ+Hsyc+Dsrb as control inputs to output addresses for automatic interpolation (the jump address and cyclic address described above) to the image memory IM.
output to the address register 26. The address generation circuit 20 will be explained in more detail below.

FIG. 4 is a diagram showing an embodiment of the address generation circuit 20, which basically constitutes a jump address generation section and a cyclic address generation section (21 and 22 in FIG. 1). The address register 26 of FIG. 3 is located on the left side of the figure, and the synchronization signal generation circuit 23 of FIG. 3 is located on the right side. Further, each single-line arrow in this figure means a flow of control signals, and each double-line arrow means a flow of control data.

In order for the address generation circuit 20 to operate, necessary parameters are first loaded in advance. This is the parameter register 30, which may be supplied from the CPUI 1 or may be manually input using a preset switch. These parameters indicate what kind of thinning is being performed.

The parameter register 30 includes a start address register (SAR) 31 and an address jump register (AJR).
32 and a line jump register (LJR) 33.

Start address register (SAR) 31 image memory 1
4. Stores the top address at which to start displaying. The display 16 displays subsequent image data from this address.

Address jump register (AJR) 3 Stores a parameter indicating the address interval on the image memory 14 in which image data for every 2 lines is stored.

Line jump register (LJR) 33 Stores a parameter indicating how many lines of image data are stored in the IM. In the example of FIG. 5, which will be described later, it is "3".

On the other hand, from the synchronization signal generation circuit 23, the already mentioned signal V□e
+ 1 (@yc and □ are supplied.

8-v The beginning of the screen display on the display 16 is shown.

Horizontal same signal Haye The beginning of the line display on the display 16 is shown.

Data strobe signal D irb From data register (25 in Figure 3) to shift register 2
Load image data one after another to display 4, and display 1 again.
Set the timing for discharging to 6.

Operating in response to each of the above signals V@VC+kc+Dsrb are working registers and counters, indicated by blocks 34, 35 and 36.

Address space accumulator (ABA) Consists of 34 addition registers and indicates the start address of a display line. This forms the main part of the jump address generation section.

Address Offset Counter (AOC) 35 Consists of an up counter, which indicates the address of a display word in a display line as an offset value from the first address in ABA 34. This forms the main part of the cyclic address generation section.

Line Jump Counter (LJC) Consists of 36 down counters and counts the amount of thinning.

FIG. 5 is a diagram schematically showing the relationship between image memory and parameters, and is a diagram showing the relationship between image memory and parameters. 1st. Each line L0. L
1. Lt... are arranged. Each hatched line contains image data, and the other lines are thinned out. Here is an example of a thinning rate of 1/3 (3
One image per book) is shown. This is the first line, and the start address (SA) corresponds to this. LJ is the amount of line jump, in this example LJ=
It becomes 3. AJ is the amount of address jump and is the product of line length (LL) and line jump (LJ).

For example, if each line has a length of 10 bytes, the address jump amount AJ will be 30 (=10×3) bytes.

The operation will be explained below.

(1) Initialize the registers using the vertical synchronization signal V syc. Start address register (SAR) 3
1 to the address space accumulator (ABA)
34. This initializes the address register 26 (FIG. 3) via the adder ADD. On the other hand, the line jump counter (LJC) 36 is cleared. In other words, the thinning counter is cleared to 0. Furthermore, the line jump amount is loaded from LJR33.

(2) Perform the following operations using the horizontal synchronization signals H,,c. First, the address offset counter (AOC) 35 is reset and its contents are set to O. In other words, the address offset is initialized. On the other hand, the line jump amount (=3) in the line jump counter (LJC) 36 is decremented by one. In other words, the number of thinning lines is -1
I'll go. As a result, when LJC36 underflows, a carry is output from it. Upon receiving this carry output, the contents (address jump amount) of the address jump register (AJR) 32 are added to the address pace accumulator (ABA) 34. Amount ABA' after addition
becomes ABA+AJR. The display line address is updated here. In addition, the line jump register (L
JR) 33 again on the line jump counter (LJ)
C) Reset to 36. In other words, the number of lines to be thinned out is initialized.

(3) The following operations are performed by the data strobe signal D m r b. First, the address in the address offset quanta (AOC) 35 is added to the address in the address pace accumulator (ABA) and the adder ADD, and the result is sent to the address register 26, and in order to designate the next pixel, The contents of the counter 35 are incremented. Note that the data strobe signal D
s r b specifies one pixel in sequence.

FIG. 6 is a timing chart showing each signal waveform from the synchronization signal generation circuit. For example, 525 horizontal synchronizing signals H@VC are generated within each cycle of the vertical synchronizing signal VllTe, and each pixel data for one line is generated within each cycle of the signal HSye by the data strobe signal D0. output in sync with

〔Effect of the invention〕

As described above, according to the present invention, an address generation circuit equipped with an automated interpolation function that is not controlled by the CPU is realized, which has the advantages of high-speed display and the ability to reduce CPU interpolation processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of an address generation circuit according to the present invention, FIG. 2 is a diagram showing an example of an image displayed by the present invention, and FIG. 3 is a diagram showing an example of the overall configuration of a video signal generation device. 4 is a diagram showing an embodiment of the address generation circuit 20, FIG. 5 is a diagram schematically showing the relationship between the image memory and parameters, and FIG. 6 is a diagram showing each signal waveform from the synchronization signal generation circuit. Timing chart, FIG. 7 is a block diagram showing the general configuration of a video display system, FIG. 8 is a diagram showing an example of an image stored in the image memory 14, and FIG. 9 is an image stored by thinning. It is a figure showing an example. 14... Image memory, 15... Video signal generator, 16... Display, 20... Address generation circuit, 21... Jump address generation section, 22... Cyclic address generation section , 23...
Synchronous signal generation circuit, Sv...video signal, Lat...data line, Lo...address line.

Claims (1)

[Claims] 1. An address generation circuit (1) that generates an address for reading image data from an image memory (14) that stores image data for each line of n (n is an integer of 2 or more) by thinning out the image data. 15) and outputs the read image data as a video signal onto the display (16) while scanning in the line order, Each time a line is scanned, a jump address generator (21) outputs an address for jumping to the address corresponding to the line where the next image data exists, and a cyclic address generation section (22) that receives an address corresponding to the line in which the immediately preceding image data exists from the jump address generation section (21) and cyclically outputs the address;
A video signal generating device comprising: accessing the image memory (14) by alternately driving the jump address generating section (21) and the cyclic address generating section (22).