JPS61130989A - X ray image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1 to which the Invention Pertains] The present invention relates to an xsi image processing device, and particularly to an xI1 image processing device capable of enlarging and reducing an image.

[Prior Art] Conventionally, in an image processing device, an image is enlarged or reduced by a microprocessor (μCPLI), or a large number of line memories or data buffer 7 memories are used to partially store the image in the memory. , by manipulating that memory. However, although this method is easy to adapt to a system with one type of image size, it is difficult to adapt to a system where many types of image sizes coexist, and extremely complex circuits (hardware) are required. Become.

[Object of the Invention] The present invention has been made in view of the above circumstances, and is intended to enable free expansion and reduction between different memory sizes in one frame (calculation time for the larger image size). In addition, the purpose is to avoid making the hardware unnecessarily complicated.

[Summary of the Invention] In order to achieve the above object, the present invention includes a plurality of image memories, a horizontal counter that receives a horizontal periodic reference signal and a count pulse and counts the count pulse, and a vertical periodic reference signal. and a vertical counter that receives count pulses and counts the count pulses; two dividers that divide the output of the horizontal counter; and two dividers that divide the output of the vertical counter. The division ratio can be controlled independently, and by outputting two sets of addresses having horizontal and vertical address information from the four dividers, and giving these two sets of addresses separately to a plurality of image memories. This is characterized in that image enlargement or reduction transfer is performed between image memories.

[Embodiment II of the invention The present invention will be described below according to embodiments with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an X-ray image processing apparatus according to the present invention. In the figure, 1 is a controller, 2 and 3 are image memories #1. #2.4 is ALU (Ar1
th metic Logic Unit) t' exists. The controller 1 can independently provide two different systems of addresses to the two image memories 2.3. The address #1 of the controller 1 for the image memory 2 will be referred to as the #2 address.

Also, the two image memories 2 and 3 are connected to each other by ALLJ4.
connected via.

FIG. 2 is a block diagram showing the internal configuration of the controller 1. As shown in FIG. In the figure, 1-1 is a horizontal counter, 1-
2 is a vertical counter, 1-3 is a divider that divides the output pulse of the horizontal counter 1-1, and 1-4 is a vertical counter 1-
A divider 1-5 divides the frequency of the output pulse of the horizontal counter 1-1, and a divider 1-6 divides the frequency of the vertical counter 1-2. The output of divider 1-3 indicates the horizontal address of #1 address,
The output of dividers 1-4 indicates the vertical address of address #1. The output of the divider 1-5 indicates the horizontal address of the #2 address, and the output of the divider 1-6 indicates the vertical address of the #2 address. 1-7 is a pulse generator,
The horizontal counter 1-1 and the vertical counter 1-2 send out a heliset signal and a clock signal to be counted.

5 is a host controller (software control unit) which gives the following parameters to the controller 1 according to the image size.

(11 groups 21' counter reset period parameters (horizontal.

Vertical) This is a control parameter for changing the horizontal cycle and the vertical four cycles according to the image size. For example, if the performance time of 1 pixel is 100ns, then 128
The image size of x128 has a horizontal period of 12.8 μs and a vertical period of 12.8 μ5×128=1.6 ms, and the host controller 5 plays the role of providing the horizontal period and vertical period. Note that this horizontal period and vertical period are NTSC (H
ational TV 5 standard coiet
You may make some changes according to the video system of the tee) method,
It can be given flexibly depending on the calculation speed of the system, etc.

(2 counter output division parameters (#1 address horizontal,
(vertical, horizontal and vertical parameters of #2 address) These parameters can be realized by giving a frequency division ratio of 2 (n-0, 1, 2, . . . ) to the divider. Thus, each divider 1-3.1-4.1-5.1-6 can be constituted by a shifter.

Next, the operation for reducing an image will be explained with reference to FIG. For example, 1024 stored in image memory 2 of #1
When reducing the image number 2 to 5122 images and storing it in the image memory 3 of #2, set the frequency division ratio of 2° to the dividers 1-3 and 1-4 to the dividers 1-5 and 1-6. against 2
Give a division ratio of 1. Figure 3 shows an example of horizontal address generation when the calculation time for one pixel is 100 ns, and the period of the output clock of horizontal counter 1-1 is 1.
00ns.

In this case, the output of the reference counter remains #
1 address, and the p1 image memory 2 that received the #1 address stores the data Do, D stored at that address.
l, 02...D1023 is output, but address #2, which is the memory address of #2 image memory 3 that takes in this data, is the output of the counter divided by 21 (that is, divided by 21). ), so as shown in Figure 3, #
1 memory 2, Dt, D3. Ds...”10
23, data is output every other time, and this data is written into the #2 memory 3. In Fig. 3, only the addresses in the horizontal direction are shown, but if the same operation is performed in the vertical direction, an image of 10242 will be converted to 5122
It is possible to reduce the size of the image to #2 and store it in the image memory 3.

In the example of L, #1 image memory 2 to Dr.

D3, Ds...D were extracted every other day and stored in the #2 image memory 3, but due to the action of the ALU 5, (DO+D')/2.
An averaging process such as (Dl +D3)/2, . . . may be performed in the horizontal and vertical directions to reduce the averaged image.

Next, the operation for enlarging an image will be explained with reference to FIG. For example, 25 written in image memory 2 of #1
When enlarging the image of No. 62 to an image size of 10,242 and storing it in the image memory 3 of #2, divider -3 of the #1 address, 22 to the divider 1-4 of the #2 address, divider 1 of the #2 address, etc.
-5°1-6 is given a divisor of 2G, and as shown in Figure 4, Do is placed at address 0.1.2.3 of #2 image memory 3, and Do is placed at address 4.5.6.7. D1 address 8.9
．． Since Dl is input to 10.11, it is possible to perform four times enlargement in the horizontal direction.

If such expansion is also performed in the vertical direction, for example, 1
A 282 size image can be easily enlarged to 10242 size and stored.

Note that if interpolation processing is performed using the ALU 5 as in the case described above, the image can be enlarged smoothly.

[Effects of the Invention] As described above, according to the present invention, two independent address series are created from the output of the reference counter using two systems of dividers, and a separate address is given to each image memory. It can be enlarged or reduced. By making it possible to appropriately switch the frequency division ratio of each divider, it becomes possible to freely control the enlargement ratio and reduction ratio.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the main parts of an X-ray image processing apparatus that is an embodiment of the present invention, FIG. 2 is a circuit block diagram showing the internal configuration of the controller of the circuit shown in FIG. 1, and FIG.
The figure is a time chart showing the reduction operation, and FIG. 4 is the time chart showing the enlargement operation. 1... Controller, 2, 3... Image memory, 1-
1...Horizontal counter, 1-2...Vertical counter, 1
-3 to 1-6... Divider.

Claims (1)

[Claims] a plurality of image memories; a horizontal counter that receives a horizontal period reference signal and count pulses and counts the count pulses; a vertical counter that receives a vertical period reference signal and count pulses and counts the count pulses; It consists of two dividers that divide the output of the horizontal counter and two dividers that divide the output of the vertical counter, and the frequency division ratio of each of the dividers can be controlled independently, and the four dividers Two sets of addresses having horizontal and vertical address information are output from the divider, and the two sets of addresses are separately given to a plurality of image memories to perform image enlargement transfer or reduction transfer between the image memories. An X-ray image processing device characterized by: