JPS62203257A - Information processor - Google Patents

Abstract

PURPOSE:To change easily the data transfer capability by executing independently respective initial setting of the desired number of data transfer means and the transfer operation according to the order of bus usage. CONSTITUTION:Plural data transfer means 4-1-4-N inserted to a path between a main memory 1 and a buffer memory 6 are subject to initial set with information such as a data start address from management section 3 and the size of a data transfer area when they are not in operation and they are started. The initial setting is executed to each of data transfer means 4-1-4-N sequentially. On the other hand, the data transfer means 4-1-4-N subject to initial set acquire the bus using right according to the lien priority decided by a main memory bus setting section 2 and a buffer memory bus setting section 5 and the data is transferred. That is, the initial set is executed while other data transfer means are in data transfer and the number of mounted data transfer means 4-1-4-N is decided flexibly depending on the size of system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that transfers data between main memory means and buffer memory means.

In particular, the present invention relates to memory access means that can easily change data transfer performance.

〔overview〕

In the data transfer means inserted between the main memory and the buffer memory, the present invention independently performs the initial setting of each of the desired number of data transfer means and the transfer operation according to the order of bus use. This allows the data transfer capability to be easily changed.

[Conventional technology]

In the conventional device, one data transfer means is interposed between the main memory means and the buffer memory means, and this transfers data, updates the addresses of the main memory means and buffer memory means, and counts the number of transferred data. .

[Problem that the invention seeks to solve]

In such conventional devices, the transfer performance is mostly determined by the hardware configuration at the time of initial design, and it is not easy to improve the transfer performance. It was also not easy to change the amount of hardware to match the transfer performance that varies from system to system.

The present invention aims to eliminate such drawbacks, and aims to provide an information processing device whose data transmission capability can be easily changed depending on the system scale.

[Means for solving problems]

The present invention provides an information processing device including a main memory, a buffer memory, and a data transfer means for transferring data between the main memory and the buffer memory based on initially set information. the number of transfer means is expandable, a management means for initializing and activating the data transfer means when data transfer from the data transfer means is in a dormant state; and the main memory and the data transfer means; A main memory bus to which the means is connected, a buffer memory bus to which the buffer memory and the data transfer means are connected, and a request to use the main memory bus from the activated data transfer means are arranged in rotational priority order. a memory bus arbitration means for permitting the use of the buffer memory bus based on rotation priority; and a memory bus arbitration means for permitting use of the buffer memory bus based on rotational priority in response to a request for use of the buffer memory bus from the activated data transfer means. The present invention is characterized by comprising a buffer memory bus arbitration means.

[Effect]

When the multiple data transfer means inserted in the path between the main memory and the buffer memory are not in operation, information such as the data start address and the size of the data transfer area is initialized by the management unit. Startup is applied. This initial setting is sequentially performed for each data transfer means.

On the other hand, the initially set data transfer means obtains the right to use the bus according to the rotation priority determined by the main memory bus adjustment section and the buffer memory bus adjustment section, and data transfer is performed. That is, the initial setting is executed while other data transfer means are transferring data. The number of data transfer means to be implemented can be flexibly determined depending on the system scale.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be explained below based on the drawings.

The figure is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. The device of this embodiment includes a main memory section 1, a main memory bus arbitration section 2, a management section 3, data transfer sections 4-1 to 4-N, a buffer memory bus arbitration section 5, a buffer memory section 6, Memory bus 7 and buffer memory bus 8
Equipped with.

First, the operation of writing data in the buffer memory section 6 to the main memory section l will be explained.

In the management section 3, information such as the data transfer start address and the size of the data transfer area of the main memory section 1 and the buffer memory section 6 are initially set. First, the management section 3 confirms that the operating display signal of the data transfer section 4-1 is the logic rOJ, and then sends the data transfer section 4-1 the write address of the main memory section 1 and the read address of the buffer memory section 6. Initialize the settings and start uplink data transfer. When the data transfer unit 4-1 is activated, the in-operation display signal is set to logic “1” and then the buffer memory bus arbitration unit 5-1
Sends a bus use request to. When bus use permission is returned from the buffer memory bus arbitration unit 5, the read address of the buffer memory unit 6 is sent to the buffer memory bus 8,
Data is read from the buffer memory unit 6 via the batho memory bus 8 and this data is held. Subsequently, the data transfer section 4-1 sends a bus use request to the main memory bus arbitration section 2. When bus use permission is returned from the main memory bus arbitration unit 2, the write address and write data of the main memory unit 1 are sent to the memory bus 7, and after the write is completed, the in-operation display signal is set to logic “0”.

On the other hand, after activating the data transfer unit 4-1, the management unit 3 updates the main memory address and the buffer memory address to point to the next transfer address, and sends an in-operation display signal to the data transfer unit 4-2. After confirming that the data transfer section 4-2 is logical "0", the data transfer section 4-2 is initialized and activated. The management unit 3 further initializes and starts up the data transfer units 4-3 and -14-H using the same procedure. Before initializing the data transfer section 4-1, check the operating display signal, and if it is not logic "0", check the logic "0".
You need to wait until ``.''

Now, each data transfer unit 4-1, 4-2, -14- in the buffer memory bus arbitration unit 5 and main memory bus arbitration unit 2
Immediately after reset, the acceptance priority of bus use requests sent from N is data transfer units 4-1, 4-2, -14.
-N, and after the data transfer unit 4-1 finishes using the bus, the data transfer units 4-2, 4-3, -・-14-
The order is N, 4-1. Thereafter, arbitration based on rotation priority will be performed in the same manner.

Through the above operations, data transfer is performed until the data transfer area of either buffer memory section 6 or main memory section 1 is exhausted.

Next, the operation of writing data in the main memory section 1 to the buffer memory section 6 will be explained. The management unit 3 confirms that the operating display signal of the data transfer unit 4-1 is logic “0” and sends the read address of the main memory unit 1 and the write address of the buffer memory unit 6 to the data transfer unit 4-1. Make the initial settings and start the downstream data transfer. When activated, the data transfer section 4-1 sets the in-operation display signal to logic "1" and then sends a bus use request to the main memory bus arbitration section 2. When bus use permission is returned from the main memory bus arbitration unit 2, the read address of the main memory unit 1 is sent to the memory bus 7, data is read from the main memory unit 1 via the memory bus 7, and this data is held. do. Subsequently, the data transfer section 4-1 sends a bus use request to the buffer memory bus arbitration section 5. When bus use permission is returned from the buffer memory bus arbitration unit 5, the write address and write data of the buffer memory unit 6 are sent to the buffer memory bus 8, and after the write is completed, the in-operation display signal is set to logic rOJ.

On the other hand, after activating the data transfer unit 4-1, the management unit 3 updates the main memory address and the buffer memory address to indicate the next transfer address, and sends an in-operation display signal to the data transfer unit 4-2. After confirming that the data transfer section 4-2 is logical "0", the data transfer section 4-2 is initialized and activated.

Thereafter, the data transfer unit 4-3 cyclically
Initialize m- in the same way, start it up, and perform data transfer.

〔Effect of the invention〕

As explained above, in the present invention, the number of data transfer units required to achieve the performance required by the system is executed, so it is possible to flexibly respond to improvements in performance or reduction in the amount of hardware. effective.

[Brief explanation of drawings]

The figure is a block configuration diagram showing the configuration of the system according to the embodiment of the present invention. 1... Main memory section, 2... Main memory bus 8
Peripheral part, 3... Management part, 4-1.4-2.4-3, -
14-N...Data transfer unit, 5...Buffer memory bus arbitration unit, 6...Buffer memory unit, 7...Memory bus, 8...Buffer memory bus.

Claims (1)

[Claims] (1) In an information processing device comprising a main memory, a buffer memory, and a data transfer means for executing data transfer between the main memory and the buffer memory based on initially set information, the data transfer method described above is provided. The number of means is a plurality of expandable means, and the management means initializes and starts the data transfer means when data transfer from the data transfer means is in a dormant state; the main memory and the data transfer means; , a buffer memory bus to which the buffer memory and the data transfer means are connected, and a request to use the main memory bus from the activated data transfer means based on the rotation priority. a memory bus arbitration means for permitting use of the memory bus based on a rotational priority order in response to a request for use of the buffer memory bus from the activated data transfer means; An information processing device comprising: buffer memory bus arbitration means.