JPS62199949U - - Google Patents
Info
- Publication number
- JPS62199949U JPS62199949U JP8873486U JP8873486U JPS62199949U JP S62199949 U JPS62199949 U JP S62199949U JP 8873486 U JP8873486 U JP 8873486U JP 8873486 U JP8873486 U JP 8873486U JP S62199949 U JPS62199949 U JP S62199949U
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor chip
- thermocompression bonding
- metal electrode
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の一実施例による半導体チツプ
仮付装置の概念図、第２図は上記実施例における
仮付け後の状態を示す断面図、第３図は熱圧着す
べき構成部分の配置状態を示す分解斜視図、第４
図は従来装置の概念図である。
１……金属電極、２……半田、３……半導体チ
ツプ、４……コレツト、５……予備加熱源、６…
…スポツト加熱源。
Fig. 1 is a conceptual diagram of a semiconductor chip tacking device according to an embodiment of the present invention, Fig. 2 is a sectional view showing the state after tacking in the above embodiment, and Fig. 3 is the arrangement of components to be bonded by thermocompression. Exploded perspective view showing the state, No. 4
The figure is a conceptual diagram of a conventional device. DESCRIPTION OF SYMBOLS 1...Metal electrode, 2...Solder, 3...Semiconductor chip, 4...Collection, 5...Preliminary heating source, 6...
...Spot heating source.
Claims (1)
する装置において、上記半田と半導体チツプとの
熱圧着工程に上記半田の一部分をスポツト加熱す
る機構を具備したことを特徴とする半導体チツプ
仮付装置。 1. An apparatus for thermocompression bonding a semiconductor chip and a metal electrode via solder, characterized in that the device is equipped with a mechanism for spot heating a portion of the solder during the thermocompression bonding process of the solder and the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8873486U JPS62199949U (en) | 1986-06-11 | 1986-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8873486U JPS62199949U (en) | 1986-06-11 | 1986-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199949U true JPS62199949U (en) | 1987-12-19 |
Family
ID=30947092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8873486U Pending JPS62199949U (en) | 1986-06-11 | 1986-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199949U (en) |
-
1986
- 1986-06-11 JP JP8873486U patent/JPS62199949U/ja active Pending