JPS62140741U - - Google Patents
Info
- Publication number
- JPS62140741U JPS62140741U JP2770886U JP2770886U JPS62140741U JP S62140741 U JPS62140741 U JP S62140741U JP 2770886 U JP2770886 U JP 2770886U JP 2770886 U JP2770886 U JP 2770886U JP S62140741 U JPS62140741 U JP S62140741U
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- lead frame
- region
- utility
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000008188 pellet Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａは本考案の一実施例のリードフレーム
にペレツトをマウントした後の概略上面図、第１
図ｂは第１図ａの概略側面図、第２図ａは従来の
リードフレームにペレツトをマウントした後の概
略上面図、第２図ｂは第２図ａの概略側面図であ
る。
１…リードフレーム、２…半田、３…ペレツト
、４…囲い、５…樹脂。
Figure 1a is a schematic top view of one embodiment of the present invention after the pellet is mounted on the lead frame;
FIG. 2b is a schematic side view of FIG. 1a, FIG. 2a is a schematic top view after the pellet is mounted on a conventional lead frame, and FIG. 2b is a schematic side view of FIG. 2a. 1...Lead frame, 2...Solder, 3...Pellet, 4...Enclosure, 5...Resin.
Claims (1)
の外側に囲いを有することを特徴とする半導体装
置。 A semiconductor device characterized by having an enclosure outside a region of a lead frame in which a pellet is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2770886U JPS62140741U (en) | 1986-02-26 | 1986-02-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2770886U JPS62140741U (en) | 1986-02-26 | 1986-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62140741U true JPS62140741U (en) | 1987-09-05 |
Family
ID=30829992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2770886U Pending JPS62140741U (en) | 1986-02-26 | 1986-02-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62140741U (en) |
-
1986
- 1986-02-26 JP JP2770886U patent/JPS62140741U/ja active Pending