JPS62198213A - Pulse control circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of the titled circuit without overlooking an input signal by widening the pulse width up to a minimum pulse width designated by a delay circuit when a narrow pulse signal is inputted. CONSTITUTION:When an input signal PI rises with outputs MLW, MHW of NAND gates 7, 8 at a high level and with an output signal PO at a low level, the output of the NAND gate 1 goes to a low level, a flip-flop consisting of NAND gates 3, 4 is set and an output signal PO goes to a high level. The output MHW of the NAND gate 8 goes to a low level and when the signal retarded by a delay circuit 6 is inputted to the NAND gate 8, the output goes again a high level. High level of the output of the NAND gate 2 continues while the output MHW is at a low level even when the input signal PI descends and the flip-flop is not reset. When the MHW goes to a high level, the flip-flop is reset and the output signal PO goes to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the control of input cavities, and more particularly to the protection of circuits that malfunction due to narrow pulse inputs.

[Conventional technology]

Conventionally, this type of circuit synchronizes input signals with a clock signal having a frequency that allows the circuit to operate.9. The internal circuit was operated by the synchronized signal.

[Problem that the invention seeks to solve]

Since the conventional circuit described above synchronizes the input signal with a clock signal, there is a possibility that an input signal with a pulse narrower than the clock signal will not be recognized. is not suitable.

[Companion means for solving problem 1] The pulse control circuit of the present invention has an output of a gate circuit whose inputs are the output of a pulse generation circuit that generates a pulse according to the fall of a desired output signal, and the input signal. and is reset by the output of a gate circuit which receives as inputs the output of a pulse generation circuit that generates a pulse in response to the rising edge of the output signal, and the output of the gate circuit.

〔Example〕

Next, the present invention is illustrated in Figure rjjJ? Refer to and explain.

FIG. 1 is a circuit diagram showing a partial block diagram of an embodiment of the present invention. NAND gate 1 has input signals PI and N
The output of AND gate 7 is input, and NAND gate 2
has the output of NAND gate 1 and the output of NAND gate 8 as inputs, and the NAND gates 3 and 4 forming the clip-flop have each other's output and the output of NAND gates 1 and 2, respectively, and all inputs, Delay circuits 5 and 6 are NAND
The output of the gate 3 is input, the gate 7 receives the output of the delay circuit 5 and the inverted signal of the output of the NAND gate 3, and the NAND gate 8 receives the inverted signal of the output of the delay circuit 6 and the inverted signal of the output of the delay circuit 6. The output of the NAND gate 3 is used as an input, and the output of the NAND gate 3 is used as the output signal PU of this embodiment.

Next, the operation will be explained with reference to the timing diagram in Figure 2.
When the input signal PI rises while the output signal PO is at a high level and the output signal PO is at a low level, the output of the N-input ND gate l becomes a low level, and the 7
Lip 70 is set and the output signal PO becomes high level. At this time, the output MHW of the NAND gate 8 becomes a low level.

The signal delayed by the delay circuit 6 is sent to the NAND gate 8.
When it is input, it becomes high level again. Even when the input No. 13 PI falls, the output of the NAND gate 2 remains at a high level while this MHW is at a low level.

Flig7og is not reset. When MHW becomes high level, the 7-rip 70-tub is reset and the output signal PO becomes low level. That is, the input signal PI
Even if the signal has a narrow pulse width, an output signal PO having a pulse width corresponding to the delay time by the delay circuit 6 can be obtained. 3 again. If input No. 13 PI rises and No. 91M MH~V remains at a high level even after reaching a high level, the output of NAND gate 1 is at a high level, the output of NAND gate 2 is at a high level, and the clip-flop is reset. Output signal PO
remains at a high level. At this time, input 1 old number PI
When becomes low level, the output of NAND gate 1 becomes high level, the output of NAND gate 2 becomes low level, and flip 7
The 0 knob is reset and the output signal PO becomes low level until the signal delayed by the output MLWf-1 delay circuit 5 of the NAND gate 7 is input to the NAND circuit 7.

Even when the input signal PI rises, while this MLW is at a low level, the output of the NAND gate 1 is at a high level and the flip-flop is not set. When MLW becomes high level, 7 lip 70 lip is set and the output signal PO becomes high level. That is, even if the input signal PI is a signal with a narrow downward pulse width, an output signal PO having a pulse width corresponding to the delay time by the delay circuit 5 can be obtained.

〔Effect of the invention〕

As explained above, the present invention prevents malfunction of the circuit without overlooking the input signal by widening the pulse width to the minimum pulse width specified by the delay circuit when a signal with a narrow pulse width is input. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. The second factor is the timing chart 1 of the embodiment shown in FIG. 1 to 4...N A +N D gate, 5.6.
...Delay circuit, 7. Total: NANI) gate with one input being an inverted input, PI: Input signal, PO: Output port number.

Claims (1)

[Claims] The output of a pulse generating circuit that generates a pulse when the desired output signal falls and the output of a gate circuit that receives the input signal as input, and the output of the pulse generating circuit that generates a pulse when the output signal rises; A pulse control circuit having a flip-flop that is reset by the output of the gate circuit that receives the output of the gate circuit as an input.