JPH0453323B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a clock signal generation method for a frequency divider that generates a frequency-divided signal synchronized with an external input signal.

In a frequency divider clock signal generation method that generates a divided signal synchronized with an external input signal, by controlling the external input signal to hide a pulse signal with a small time width that appears at the rise of the frequency divider output. , it may be necessary to prevent malfunctions based on pulse signals with a small time width.

[Industrial application field]

The present invention relates to a clock signal generation system for a frequency divider that generates a frequency-divided signal synchronized with an external input signal.

In each device that constitutes a data processing device system, it is often necessary to generate a signal called a clock signal that serves as a timing reference within each device to synchronize the operation of the circuit with the operation of other devices. In this case, an external input signal is received from another device, and the external input signal and the clock signal are synchronized.

Generally, when synchronizing an external input signal and a clock signal, the required clock signal is generated by dividing a high-frequency basic signal, and the frequency division operation is controlled according to the input conditions of the external input signal to generate the clock signal. get. A counter is used as a frequency divider for this frequency dividing means, but at the beginning of generation of the frequency divided signal, a pulse signal with a time width shorter than the required time width may be output, which may cause malfunction.

For this reason, there is a need for a clock signal generation system that prevents the output of this short-time signal.

[Conventional technology]

FIG. 3 is a block diagram of a conventional clock signal generation system, and FIG. 4 is a waveform diagram.

The basic signal A generated by the basic signal generator 1 is connected to the flip-flop circuits 3 and 4 and the frequency divider 6 forming the synchronous sampling signal generating circuit 2.
Enter each into CL. Further, an external input signal B is input to the flip-flop circuit 3.

Assuming that the external input signal B has now become "1", the flip-flop circuit 3 punches out the external input signal B at the rising timing of the basic signal A next to the rising timing at which the external input signal B becomes "1", and changes it to "0". ” to “1” is generated. Similarly, this synchronous sampling signal C is input to the d terminal of the flip-flop circuit 4 and punched out at the rising edge of the basic signal A, and at a timing delayed by one basic signal A time width from the rising timing of the synchronous sampling signal C. Outputs a signal X that changes from "1" to "0".

This signal Add it to the load terminal L of the device 6. The frequency divider 6 is once reset to "0" by the load signal Y from the two-input AND NOT circuit 5, and then starts counting the basic signal A and reaches a predetermined count value. A frequency-divided signal D is sent from an output terminal Q. Note that this frequency-divided signal D is
The following two shapes are available depending on the timing of the basic signal A and the load signal Y.

That is, when the load signal Y is input at the timing after the frequency divider 6 changes from "0" to "1",
The output of the frequency divider 6 is 1 after the time width of the “1”.
The time of the basic signal A is reset to "0", and from then on, normal counting starts from "0" (Fig. 4 Y
(indicates the load signal Y generated when the load signal Y is input at the timing when the frequency divider 6 changes from "0" to "1"). In this case, the frequency-divided signal D generates a positive polarity short-time pulse signal.

Also, when the load signal Y is input at a timing after the frequency divider 6 changes from "1" to "0", the frequency divider 6 inputs one basic signal after the time width of "0". The time A is reset to "0", and from then on, a normal counting operation starts from "0". in this case,
In the frequency-divided signal D, no short-time pulse signal of positive polarity is generated.

[Problems to be Solved by the Invention] In the conventional method described above, depending on the timing of the external input signal and the basic signal A, the divided signal D may have a
A short-time pulse signal of positive polarity corresponding to the basic signal may be generated. Such short-width pulses are
This may cause the subsequent circuit connected to the frequency divider 6 to malfunction.

Furthermore, in order to ensure normal operation even with such short-width pulse signals, it is necessary to change to a high-speed operation circuit, which is an economical problem.

The present invention was created in view of the above points, and by outputting an OR signal of the control signal E and the frequency division signal D that covers the period up to the first rising edge of the frequency divider 6, It is an object of the present invention to provide a clock signal generation method that prevents the output of a pulse signal having a time width.

[Means to solve the problem]

FIG. 1 is a basic block diagram of the clock signal generation system of the present invention.

In the figure, 1 is a basic signal oscillator, 2 is a synchronous sampling signal generation circuit comprising flip-flop circuits 3 and 4 and a 2-input AND/NOT output circuit 5;
6 is a frequency divider, 7 is a control signal circuit for concealing a short-time pulse signal, and 8 is an OR circuit.

A control signal circuit 7 and an OR circuit 8 are added to the circuit constituted by symbols 1 to 6 shown in the conventional example, and the input of the control signal circuit 7 is connected to the L terminal of the frequency divider 6. The circuit is constructed such that the output of the conventional circuit and the output of the control signal circuit 9 are logically summed in an OR circuit 8 and a clock signal is extracted.

[Effect]

As shown by waveform E in the waveform diagram of FIG. 4, the control signal E generated by the control signal circuit 7 rises at the same time as the synchronous sampling signal C, and becomes "0" at the first rise of the output of the frequency divider 6. It's a signal.

Therefore, by ORing the frequency-divided signal D and the control signal E in the OR circuit 8,
A clock signal F can be obtained in which the short-time pulse signal appearing in the frequency-divided signal D is concealed.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the clock signal generation system of the present invention. Note that the waveforms in the present invention are shown in E and F in FIG. Also, the same reference numerals indicate the same objects throughout the figures.

The control signal circuit 7 includes a NOT circuit 10, 2-input AND AND NOT circuits 11, 12, and 2-NOT input OR circuit 1.
It consists of a 3,3 NOT input OR circuit 14. 8 again
is an OR circuit.

The load signal Y of the frequency divider 6 simultaneously becomes one input of the two-input AND NOT circuit 12, and the NOT circuit 10
It becomes one input of the 2-input AND NOT circuit 11 via.

The other input of the 2-input AND NOT circuit 11 is connected to the frequency divider 6 along with one input of the 2-input AND NOT circuit 12.
connected to the output of

The outputs of the 2-input AND/NOR circuits 11 and 12 become inputs to the NATION input OR circuits 13 and 14, respectively, and the NATION input OR circuits 13 and 14 form a flip-flop in which each other's output and one input are crossed and connected. However, the 2-NOT input OR circuit 13 becomes the signal E shown in FIG. 4, which is the output of the control signal circuit 7. Note that one input of the 3-NOT input OR circuit 14 receives a reset signal that guarantees the logic when the power is turned on.

The divided signal D which is reset by the load signal Y and output from the frequency divider 6 rises in synchronization with the load signal and is turned off at the timing when the output of the frequency divider 6 rises for the first time after being reset. The logic of the control signal E is logically summed by the summation circuit 9, and the divided signal D is hidden, and the logical sum signal F shown in FIG. 4 becomes the clock signal to the external circuit.

Moreover, "1" and "0" of the above-mentioned signals are expressed in the same way as H level (on) and L level (off) in a logic circuit.

〔Effect of the invention〕

As described above, according to the present invention, a control signal can be generated using a simple circuit added to a conventional output signal, and short-time width pulses can be hidden, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the synchronization signal generation system of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention,
Figure 3 is a block diagram of the conventional example, Figure 4 is a waveform diagram,
It is. In the figure, 1 is a basic signal oscillator, 2 is a synchronous sampling signal generation circuit, 6 is a frequency divider, 7 is a control signal circuit, 8 is an OR circuit, A is a basic signal, B is an external input signal, and C is synchronous sampling D is a frequency division signal, E is a control signal, and F is an OR signal (clock signal).

Claims (1)

[Claims] 1. Basic signal oscillator 1 that outputs a reference basic signal.
a synchronous sampling signal generation circuit 2 that outputs a load signal that rises in synchronization with the basic signal according to an external input signal and has a signal width equal to one period of the basic signal; and a synchronous sampling signal generation circuit 2 that is reset and frequency-divided by the load signal In a clock signal generation system including a frequency divider 6 that generates an output, a control signal is output that rises in synchronization with the load signal and turns off at the timing of the first rise after the output of the frequency divider 6 is reset. A clock signal generation method characterized in that a control signal circuit 7 is provided, and an OR circuit 8 is provided for ORing the control signal and the frequency-divided output, and the output of the OR circuit 8 is used as a clock signal. .