JPS6219752U - - Google Patents
Info
- Publication number
- JPS6219752U JPS6219752U JP11117385U JP11117385U JPS6219752U JP S6219752 U JPS6219752 U JP S6219752U JP 11117385 U JP11117385 U JP 11117385U JP 11117385 U JP11117385 U JP 11117385U JP S6219752 U JPS6219752 U JP S6219752U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- package
- same direction
- external lead
- lead rows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の実施例を示した半導体集積回
路装置用セラミツクパツケージの外観図、第２図
は第１図に示したパツケージのプリント基板への
実装図、第３図は従来パツケージの外観図、第４
図は第３図に示したパツケージのプリント基板へ
の実装図である。
１，１１……半導体集積回路装置用セラミツク
パツケージ本体、２，１２……同上の最も広い面
、３，４，１３，１４……同上の外部リード列、
５，１５……同上のプリント基板への実装面、６
，１６……プリント基板。
Fig. 1 is an external view of a ceramic package for a semiconductor integrated circuit device showing an embodiment of the present invention, Fig. 2 is an illustration of the package shown in Fig. 1 mounted on a printed circuit board, and Fig. 3 is an external view of a conventional package. Figure, 4th
The figure is a diagram showing how the package shown in FIG. 3 is mounted on a printed circuit board. 1, 11... Ceramic package body for semiconductor integrated circuit device, 2, 12... Widest surface as above, 3, 4, 13, 14... External lead row as above,
5, 15... Mounting surface on the same printed circuit board, 6
, 16...Printed circuit board.
Claims (1)
集積回路装置用セラミツクパツケージにおいて、
前記同一向きの２つの外部リード列がパツケージ
本体の最も広い面に対して平行に出ていることを
特徴とする集積回路パツケージ。 In a ceramic package for a semiconductor integrated circuit device having two external lead rows oriented in the same direction,
An integrated circuit package characterized in that the two external lead rows facing the same direction extend parallel to the widest surface of the package body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11117385U JPS6219752U (en) | 1985-07-19 | 1985-07-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11117385U JPS6219752U (en) | 1985-07-19 | 1985-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6219752U true JPS6219752U (en) | 1987-02-05 |
Family
ID=30990849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11117385U Pending JPS6219752U (en) | 1985-07-19 | 1985-07-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6219752U (en) |
-
1985
- 1985-07-19 JP JP11117385U patent/JPS6219752U/ja active Pending