JPS62194684A - Semiconductor light-receiving device - Google Patents

Semiconductor light-receiving device

Info

Publication number
JPS62194684A
JPS62194684A JP61036261A JP3626186A JPS62194684A JP S62194684 A JPS62194684 A JP S62194684A JP 61036261 A JP61036261 A JP 61036261A JP 3626186 A JP3626186 A JP 3626186A JP S62194684 A JPS62194684 A JP S62194684A
Authority
JP
Japan
Prior art keywords
substrate
layer
receiving device
metal electrodes
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61036261A
Other languages
Japanese (ja)
Inventor
Masanori Ito
正規 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61036261A priority Critical patent/JPS62194684A/en
Publication of JPS62194684A publication Critical patent/JPS62194684A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To lessen a dark current of a light-receiving device by a method wherein a pair of metal electrodes containing impurities of one conductivity type, which are formed on a semiconductor layer of the other conductivity type connected on a substrate, are alloyed to form a horizontal-type alloyed transistor structure. CONSTITUTION:The device is constructed in such a manner that, an SI-GaAs substrate 1 being used as a substrate, alloy barriers are formed by paired metal electrodes 5 and 6 on an n-GaAs layer 2 of thickness 3mum, a semiconductor layer (light-absorbing layer), connected on the substrate. The metal electrodes 5 and 6 are alloyed respectively by a method wherein a gold zinc (AuZn, Zn 5%) layer of thickness 2,000Angstrom having fifteen comb teeth of width 3mum disposed at an interval of 9mum is heated at 450 deg.C for 3min. The metal electrodes 5 and 6 are so disposed as to be spaced at 3mum from each other.

Description

【発明の詳細な説明】 〔概要〕 0.8〜1.6μm帯の光通信用半導体受光装置を含む
光電子集積回路(OEIC)に用いられる、ショットキ
(Schottky)電極を有するMSN−PD(Me
tal−Semiconductor−Metal P
hotodetector)を合金、または拡散により
横型トランジスタ化した構造を提起して、受光装置の暗
電流を減少させることができた。
Detailed Description of the Invention [Summary] MSN-PD (Me
tal-Semiconductor-Metal P
By developing a structure in which a photodetector is made into a lateral transistor by alloying or diffusion, the dark current of the photodetector can be reduced.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体受光装置に係り、?lSM−PDを改良
した構造に関する。
The present invention relates to a semiconductor light receiving device. This invention relates to a structure that is an improved version of lSM-PD.

従来のフォトディテクタでは、PIN(p型半導体−絶
縁層−n型半導体)ダイオードやAI’D(Avala
nche Photodiode)等のバルク構造の素
子が多く用いられていた。
Conventional photodetectors use PIN (p-type semiconductor-insulating layer-n-type semiconductor) diodes and AI'D (Avala diode).
Elements with a bulk structure, such as photodiodes (photodiodes), were often used.

一方、MSN−PDは表面構造の素子で、構造が簡単で
集積が容易である。例えば電界効果トランジスタ(FE
T)と集積する場合は、ゲート金属の蒸着と同時にMS
M−PDを形成できる等の利点がある。
On the other hand, MSN-PD is a surface-structured device, which has a simple structure and is easy to integrate. For example, field effect transistor (FE)
When integrating with T), MS is applied at the same time as gate metal evaporation.
It has advantages such as being able to form an M-PD.

しかしながら、MSN−PDはショットキ障壁の形成が
難しく、上記のバルク構造の素子に比し暗電流が大きく
なりやすい欠点があり、改善が望まれている。
However, MSN-PDs have drawbacks in that it is difficult to form a Schottky barrier and dark current tends to be large compared to the above-mentioned bulk structure elements, and improvements are desired.

〔従来の技術〕[Conventional technology]

第5図(1)、(2)はそれぞれ従来例による0、8μ
m帯のMSM−PDの断面図、平面図である。
Figure 5 (1) and (2) are respectively 0 and 8μ according to the conventional example.
FIG. 2 is a cross-sectional view and a plan view of an m-band MSM-PD.

第5図1))において、半絶縁性ガリウム砒素(Sl−
GaAs)基板1上に被着された光吸収層のn型GaA
s(n−GaAs)層2とアルミニウム(八り電極3.
4でショットキ障壁を形成してMSM−PDは構成され
る。
In Fig. 5 1)), semi-insulating gallium arsenide (Sl-
n-type GaAs) as a light absorption layer deposited on the substrate 1
s (n-GaAs) layer 2 and aluminum (eight electrode 3.
The MSM-PD is constructed by forming a Schottky barrier in step 4.

第5図(2)において、AI電極3と4はそれぞれ櫛型
に、その歯は交互に入り組んで形成されている。
In FIG. 5(2), the AI electrodes 3 and 4 are each formed in a comb shape, with teeth intertwined alternately.

第5図(1)はA−A断面を示す。FIG. 5(1) shows the AA cross section.

このように電極の櫛型構成により、大きな受光面積が得
られる。
As described above, the comb-shaped structure of the electrodes provides a large light-receiving area.

第6図は従来例による1、3〜1.6μm帯のMSM−
PDの断面図である。
Figure 6 shows a conventional MSM in the 1, 3 to 1.6 μm band.
It is a sectional view of PD.

図において、半絶縁性インジウムR(Sl−InP)基
板ll上に被着され、InPと格子整合する組成を有す
る光吸収層としてのインジウムガリウム砒素(Ino、
 s:+Gao、 =7As)層12とAt電極13.
14でショットキ障壁を形成してMSM−PDは構成さ
れる。
In the figure, indium gallium arsenide (INO,
s:+Gao, =7As) layer 12 and At electrode 13.
The MSM-PD is constructed by forming a Schottky barrier in step 14.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のMSM−PDは、ショットキ障壁の高さが低く、
暗電流が大きい。
Conventional MSM-PD has a low Schottky barrier height,
Dark current is large.

とくに、InP系の半導体はショットキ障壁の形成が困
難である。
In particular, it is difficult to form a Schottky barrier in InP-based semiconductors.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、基板上に被着された一導電型半導
体層上に、一対の他導電型不純物を含む金属電極を合金
化して横型合金トランジスタ構造とした半導体受光装置
、あるいは 基板上に被着された一導電型半導体層に、一対の他導電
型不純物導入領域を形成し、該領域上に金属電極を形成
して横型拡散トランジスタ構造とした半導体受光装置に
より達成される。
The solution to the above problem is to create a semiconductor photodetector device that has a horizontal alloy transistor structure by alloying a pair of metal electrodes containing impurities of the other conductivity type on a semiconductor layer of one conductivity type deposited on a substrate, or This is achieved by forming a pair of impurity-introduced regions of the other conductivity type in the deposited semiconductor layer of one conductivity type, and forming a metal electrode on the regions to form a semiconductor light receiving device having a lateral diffusion transistor structure.

〔作用〕[Effect]

第3図は従来のMSN−PDのエネルギ準位図である。 FIG. 3 is an energy level diagram of a conventional MSN-PD.

図示されるように、MSN−PDでは接合にショットキ
障壁を用いているため、暗電流を左右する電極(アノー
ド、およびカソード)の障壁高さφ7、φ、は半導体層
の禁制帯幅E、よりも小さく、約(1/2)E、である
As shown in the figure, since the MSN-PD uses a Schottky barrier in the junction, the barrier heights φ7 and φ of the electrodes (anode and cathode), which affect the dark current, are smaller than the forbidden band width E of the semiconductor layer. is also small, approximately (1/2)E.

第4図は本発明の横型トランジスタ構造の受光装置のエ
ネルギ準位図である。
FIG. 4 is an energy level diagram of a light receiving device having a lateral transistor structure according to the present invention.

この場合は、半導体の伝導帯下端をフェルミ準位に合わ
せると、暗電流を左右する合金、または拡散接合の障壁
高さφ7、φ=は半導体層の禁制帯幅E9に略等しい。
In this case, when the lower end of the conduction band of the semiconductor is adjusted to the Fermi level, the barrier height φ7, φ= of the alloy or diffusion junction that influences the dark current is approximately equal to the forbidden band width E9 of the semiconductor layer.

このように、本発明では障壁高さを高くして、暗電流を
従来の?ISM−PDより減少させることができる。
In this way, in the present invention, the barrier height is increased and the dark current is lower than that of the conventional one. It can be reduced compared to ISM-PD.

なお、接合の完全性より、暗電流低減には合金接合より
拡散接合の方が一層効果がある。
Note that diffusion bonding is more effective in reducing dark current than alloy bonding in terms of bonding integrity.

〔実施例〕〔Example〕

第1図は本発明による0、8μm帯の横型合金トランジ
スタ構造の受光装置の断面図である。
FIG. 1 is a sectional view of a light receiving device having a 0.8 μm band horizontal alloy transistor structure according to the present invention.

図において、基板として5l−GaAs基板1を用い、
その上に被着された半導体層(光吸収層)の厚さ3μm
のn  GaAs層2に、一対の金属電極5.6で合金
障壁を形成して構成される。
In the figure, a 5l-GaAs substrate 1 is used as the substrate,
The thickness of the semiconductor layer (light absorption layer) deposited on it is 3 μm
An alloy barrier is formed on the n-GaAs layer 2 by a pair of metal electrodes 5.6.

金属電極5.6はそれぞれ、第5図(2)のように、1
5本の幅3μmの櫛歯を間隔9μmに配設された厚さ 
2000人の金亜鉛(AuZn、 Zn5%)層を45
0℃で3分加熱して合金化する。
Each of the metal electrodes 5.6 is 1 as shown in FIG. 5(2).
Five comb teeth with a width of 3 μm arranged at a spacing of 9 μm.
2000 gold zinc (AuZn, Zn5%) layers 45
Alloy by heating at 0°C for 3 minutes.

金属電極5.6の相互の間隔は3μmに配置する。The metal electrodes 5.6 are arranged at a mutual interval of 3 μm.

第2図は本発明による0、8μm帯の横型拡散トランジ
スタ構造の受光装置の断面図である。
FIG. 2 is a sectional view of a light-receiving device having a lateral diffusion transistor structure in the 0.8 μm band according to the present invention.

図において、5l−GaAs基板1の上に被着された厚
さ3μmのn −GaAs層 2に、一対のp型不純物
導入領域7.8による拡散障壁を形成して構成される。
In the figure, an n-GaAs layer 2 with a thickness of 3 μm is deposited on a 5l-GaAs substrate 1, and a diffusion barrier is formed by a pair of p-type impurity doped regions 7.8.

p型不純物導入領域7.8はそれぞれ、第5図(2)の
ように、15本の幅3μmの櫛歯を間隔9μmに形成さ
れた深さ0.5〜1μmの亜鉛(Zn)拡散層である。
Each p-type impurity-introduced region 7.8 is a zinc (Zn) diffusion layer with a depth of 0.5 to 1 μm formed with 15 comb teeth each having a width of 3 μm and an interval of 9 μm, as shown in FIG. 5(2). It is.

p型不純物導入領域7.8の相互の間隔は3μmに配置
する。
The p-type impurity introduced regions 7.8 are arranged at a mutual interval of 3 μm.

Zn拡散は、パターニングされた厚さ1000人の窒化
珪素(Si3N4)層をマスクにして、500〜600
℃で行う。
Zn diffusion was performed using a patterned silicon nitride (Si3N4) layer with a thickness of 500 to 600 nm as a mask.
Perform at °C.

p型不純物導入領域7.8の上にAuZn電極9.10
を形成する。
AuZn electrode 9.10 on p-type impurity introduced region 7.8
form.

従来のMSM−PDの暗電流は100 /J A程度で
あったが、以上の実施例においてはこれより1〜2桁小
さくなった。
The dark current of a conventional MSM-PD was about 100/JA, but in the above embodiments it was one to two orders of magnitude smaller than this.

実施例においては、半導体層にGaAsを用いたが、こ
れの代わりにInGaAs %アルミニウムインジウム
砒素(^l InAs)等その他の半導体層を用いても
よい。
In the embodiment, GaAs is used for the semiconductor layer, but other semiconductor layers such as InGaAs% aluminum indium arsenide (^l InAs) may be used instead.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、受光装置の暗電流
は小さくなる。
As explained above, according to the present invention, the dark current of the light receiving device is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による0、8μm帯の横型合金トランジ
スタ構造の受光装置の断面図、 第2図は本発明による0、8μm帯の横型拡散トランジ
スタ構造の受光装置の断面図、 第3図は従来のMSM−PDのエネルギ準位図、第4図
は本発明の横型トランジスタ構造の受光装置のエネルギ
準位図、 第5図(1)、(2)はそれぞれ従来例による0、8μ
m帯のMSM−PDの断面図、平面図、 第6図は従来例による1、3〜1.6μm帯のMSN−
PDの断面図である。 図において、 lは基板で5l−GaAs基板、 2は一導電型半導体層でn −GaAs層、5.6は金
属(AuZn)電極、 7.8は他導電型不純物導入領域で p型不純物導入領域、 9、lOは金属(AuZn)電極 $5図 準乙囚 図面の一争ご(内πに変更なし) 手続補正書□ 061年撰−第36261号 2、発明の名称 半導体受光装置 3、補正をする者 事件との関係  特許出願人 住所 神奈川県用崎市中厚区上小田中1015番地(5
22)名称富士通株式会社 4、代理人 住所 神奈川県川崎市中原区上小田中1015番地富士
通株式会社内 )il1社のとおり
FIG. 1 is a sectional view of a light receiving device with a lateral alloy transistor structure in the 0.8 μm band according to the present invention. FIG. 2 is a cross sectional view of a light receiving device with a lateral diffused transistor structure in the 0.8 μm band according to the present invention. FIG. 4 is an energy level diagram of a conventional MSM-PD, FIG. 4 is an energy level diagram of a light receiving device with a lateral transistor structure of the present invention, and FIGS. 5 (1) and (2) are 0 and 8μ according to the conventional example, respectively
A cross-sectional view and a plan view of an m-band MSM-PD.
It is a sectional view of PD. In the figure, l is the substrate, which is a 5l-GaAs substrate, 2 is a semiconductor layer of one conductivity type, which is an n-GaAs layer, 5.6 is a metal (AuZn) electrode, and 7.8 is an impurity introduction region of another conductivity type, where p-type impurities are introduced. Area, 9, IO is a dispute over the drawing of a metal (AuZn) electrode $5 (no change in π) Procedural amendment □ Drafted in 061 - No. 36261 2, Name of the invention Semiconductor photodetector device 3, Relationship with the case of the person making the amendment Patent applicant address 1015 Kamiodanaka, Nakaatsu-ku, Yozaki City, Kanagawa Prefecture (5
22) Name: Fujitsu Limited 4, Agent Address: 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited) As per il1 company

Claims (2)

【特許請求の範囲】[Claims] (1)基板上に被着された一導電型半導体層上に、一対
の他導電型不純物を含む金属電極を合金化してなること
を特徴とする半導体受光装置。
(1) A semiconductor light-receiving device characterized by comprising a semiconductor layer of one conductivity type deposited on a substrate and a pair of metal electrodes containing impurities of the other conductivity type alloyed together.
(2)基板上に被着された一導電型半導体層に、一対の
他導電型不純物導入領域を形成し、該領域上に電極を形
成してなることを特徴とする半導体受光装置。
(2) A semiconductor light-receiving device characterized in that a pair of impurity-introduced regions of the other conductivity type are formed in a semiconductor layer of one conductivity type deposited on a substrate, and an electrode is formed on the regions.
JP61036261A 1986-02-20 1986-02-20 Semiconductor light-receiving device Pending JPS62194684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61036261A JPS62194684A (en) 1986-02-20 1986-02-20 Semiconductor light-receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61036261A JPS62194684A (en) 1986-02-20 1986-02-20 Semiconductor light-receiving device

Publications (1)

Publication Number Publication Date
JPS62194684A true JPS62194684A (en) 1987-08-27

Family

ID=12464823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61036261A Pending JPS62194684A (en) 1986-02-20 1986-02-20 Semiconductor light-receiving device

Country Status (1)

Country Link
JP (1) JPS62194684A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927991A (en) * 1972-05-30 1974-03-12
JPS55102281A (en) * 1978-11-30 1980-08-05 Gen Electric Radiationnsensitive transistor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927991A (en) * 1972-05-30 1974-03-12
JPS55102281A (en) * 1978-11-30 1980-08-05 Gen Electric Radiationnsensitive transistor device

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