JPS62104178A - Pin photo diode - Google Patents

Pin photo diode

Info

Publication number
JPS62104178A
JPS62104178A JP60244418A JP24441885A JPS62104178A JP S62104178 A JPS62104178 A JP S62104178A JP 60244418 A JP60244418 A JP 60244418A JP 24441885 A JP24441885 A JP 24441885A JP S62104178 A JPS62104178 A JP S62104178A
Authority
JP
Japan
Prior art keywords
layer
conductivity type
grown
gaas
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60244418A
Other languages
Japanese (ja)
Inventor
Shuichi Miura
秀一 三浦
Osamu Wada
修 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60244418A priority Critical patent/JPS62104178A/en
Publication of JPS62104178A publication Critical patent/JPS62104178A/en
Pending legal-status Critical Current

Links

Landscapes

  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To enable fast response by sequentially growing one conductivity type contact layer and one conductivity type optical absorption layer 3 on a substrate, and selectively removing both layers so that no n<+> region exists under the bonding pad, thereby reducing the capacitance. CONSTITUTION:On a Si-GaAs substrate 1, an n<+>-GaAs layer 2 as a contact layer and an n<->-GaAs layer 3 as an optical absorption layer are sequentially grown, selective etching is performed leaving the photo detecting portion of the layer 3, and selective etching is performed leaving the photo detecting portion of the layer 2 and the n-side bonding pad portion. Then, an n<->-Al0.3 Ga0.7As layer 4 as a high-resistance layer (window layer) is grown, and using as a mask a Si3N4 layer 6 formed on the surface of the layer 4 by etching, Zn is diffused to form a p<+> type region 5. A p-side ohmic electrode 8 containing the bonding pad therein and composed of Ti/Pt/Au is formed surrounding a photo detecting portion 7, and an n-side ohmic electrode 9 of AuGe/Au if formed on the layer 2. Since overlapping of the layer 2 and the electrode 8 is eliminated is both, unnecessary capacitance except for the photo detecting portion is reduced, enabling the capacitance of the whole pin diode to be reduced.

Description

【発明の詳細な説明】 〔概要〕 高速のpinホトダイオードを得るため、受光部領域以
外の、すなわちボンデイングノイ・ノド部の容量を低減
することにより、pinホトダイオードの容量を減らす
構造を提起する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] In order to obtain a high-speed pin photodiode, a structure is proposed in which the capacitance of the pin photodiode is reduced by reducing the capacitance in areas other than the light receiving area, that is, in the bonding node area.

〔産業上の利用分野〕[Industrial application field]

本発明は容量低減の改善を行ったpinホトダイオード
の構造に関する。
The present invention relates to a pin photodiode structure with improved capacity reduction.

光通信の高速、大容量化を目的として、受光素子の高速
化の研究が活発になされている。
With the aim of increasing the speed and capacity of optical communications, research into increasing the speed of light-receiving elements is being actively conducted.

特に、pinホトダイオードの応答速度を制限するもの
はこれの持つ(静電)容量と空乏層中のキャリアの走行
時間であり、とくに容量を小さくすることは高速化のた
めに極めて重要である。
In particular, what limits the response speed of a pin photodiode is its (electrostatic) capacitance and the travel time of carriers in the depletion layer, and reducing the capacitance is particularly important for increasing speed.

〔従来の技術〕[Conventional technology]

第3図(1)、(2)は従来例によるpinホトダイオ
ードの斜視図、断面図である。
FIGS. 3(1) and 3(2) are a perspective view and a sectional view of a conventional pin photodiode.

ここで図番は、第1図との対比の便宜のため、31を欠
番とする。
Here, the figure number 31 is omitted for convenience of comparison with FIG. 1.

第3図(1)において、n1型ガリウム砒素(n ”−
GaAs)基板32上に、 光吸収層としてn−型ガリウム砒素 (n ’−GaAs)層33、 ウィンド層としてn−型アルミニウムガリウム砒素(n
−Alo、 3Gao、 ?AS)層34を順次成長す
る。
In Figure 3 (1), n1 type gallium arsenide (n ”-
An n-type gallium arsenide (n'-GaAs) layer 33 is formed as a light absorption layer on a substrate 32, and an n-type aluminum gallium arsenide (n'-GaAs) layer 33 is formed as a window layer on a substrate 32.
-Alo, 3Gao, ? AS) layers 34 are grown sequentially.

つぎに、n−Alo、 5Gao、 ?AS層34の表
面に形成された窒化珪素(SiJ*)層36をマスクに
して亜鉛(Zn)を拡散してp°型領領域35形成する
Next, n-Alo, 5Gao, ? Using a silicon nitride (SiJ*) layer 36 formed on the surface of the AS layer 34 as a mask, zinc (Zn) is diffused to form a p° type region 35.

なお、Si、IN4層36はバフシベーシッン膜として
そのまま残しておく。
Note that the Si, IN4 layer 36 is left as it is as a buffing basin film.

つぎに、p゛型領領域35内ポンディングパッド38^
を含み、チタン/白金/金(Ti/Pt/Au)よりな
るp側オーミック電極38を受光部37の周囲に形成す
る。
Next, the bonding pad 38^ in the p type region 35
A p-side ohmic electrode 38 made of titanium/platinum/gold (Ti/Pt/Au) is formed around the light receiving part 37.

n ”−GaAs基Fi32の裏面に金ゲルマニウム/
金(AuGe/Au)よりなるn側オーミック電極39
を形成する。
n''-gold germanium/on the back side of GaAs-based Fi32
N-side ohmic electrode 39 made of gold (AuGe/Au)
form.

第3図(2)において、p“型領域35はウィンド層で
ある高抵抗のn−^16.5Gao、 tAs層34の
厚さ一杯に形成されている。
In FIG. 3(2), the p" type region 35 is formed to the full thickness of the high resistance n-^16.5 Gao, tAs layer 34 which is a window layer.

この構造の場合、受光部に加えてポンディングパッドの
領域もZn拡散を行っているため、接合面積が広くなり
、容量が大きくなるという欠点がある。
In this structure, since Zn is diffused in the bonding pad region in addition to the light receiving portion, there is a drawback that the bonding area becomes large and the capacitance becomes large.

また、これを改善してポンディングパッドはZn拡散を
行っていない領域に形成する、すなわちバンシベーショ
ン膜上に形成する方法があるが、このようにしてもポン
ディングパッドの下部にはn″領域32が存在し、顕著
な容量の低減化はなされていない。
In addition, there is a method to improve this and form the bonding pad in a region where Zn is not diffused, that is, to form it on the bancivation film, but even with this method, there is an n'' region under the bonding pad. 32, and there is no significant reduction in capacity.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来構造のpinホトダイオードでは、比較的大面積を
占めるポンディングパッド領域の容!低減がなされてい
なかった。
In a pin photodiode with a conventional structure, the bonding pad area occupies a relatively large area! No reduction had been made.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、基i (1)上に一導電型コンタ
クト層(2)と、一導電型光吸収層(3)を順次成長し
、該光吸収層(3)とコンタクト層(2)を選択的に除
去した後、該コンタクト層(2)より抵抗値の高い高抵
抗I’! (41を成長し、該光吸収層(3)上の該高
抵抗層(4)を他導電型領域(5)に変換し、一導電型
コンタクト層(2)と他導電型領域(5)上に電極を形
成してなるpinホトダイオード、および 基板(1)上に一導電型4ンタクト層(2)を成長し、
該コンタクト層(2)を選択的に除去した後、光吸収層
(3)と、該コンタクト層(2)より抵抗値の高い高抵
抗N(4)とを成長し、受光領域を含んで選択的に該高
抵抗層(4)を他導電型領域(5)に変換し、一導電型
コンタクト層(2)と他導電型領域(5)上に電極を形
成してなるpinホトダイオードにより達成される。
The above problem can be solved by sequentially growing a contact layer (2) of one conductivity type and a light absorption layer (3) of one conductivity type on the substrate i (1). ) is selectively removed, a high resistance I'! whose resistance value is higher than that of the contact layer (2) is formed. (41), converting the high resistance layer (4) on the light absorption layer (3) into a region (5) of another conductivity type, and forming a contact layer (2) of one conductivity type and a region (5) of another conductivity type. A pin photodiode with an electrode formed thereon, and a four-conductivity type contact layer (2) grown on the substrate (1),
After selectively removing the contact layer (2), a light absorption layer (3) and a high resistance layer N (4) having a higher resistance value than the contact layer (2) are grown and selected including the light receiving region. This is achieved by converting the high resistance layer (4) into a region (5) of a different conductivity type and forming an electrode on a contact layer (2) of one conductivity type and a region (5) of a different conductivity type using a pin photodiode. Ru.

〔作用〕[Effect]

本発明はポンディングパッドの下部にはn″領域存在し
ないように、基板上にn′層を成長し、該層を選択的に
除去することにより容量の低減をはかったものである。
The present invention aims at reducing capacitance by growing an n' layer on a substrate so that there is no n'' region under the bonding pad and selectively removing this layer.

〔実施例〕〔Example〕

第1図は第1の発明によるpinホトダイオードの断面
図である。
FIG. 1 is a sectional view of a pin photodiode according to the first invention.

図において、 (11例えば、有機金属化学気相成長(MOCVD)法
により、半絶縁性ガリウム砒素(SI−GaAs)基板
1上に、 コンタクト層としてキャリア濃度I X 10’ ”c
nr’、厚さ2μmのn ’−GaAs層2と、光吸収
層としてキャリア濃度5X1014cm−”、厚さ4μ
mのn−GaAs層3 を順次成長する。
In the figure, (11) is deposited as a contact layer on a semi-insulating gallium arsenide (SI-GaAs) substrate 1 by, for example, metal organic chemical vapor deposition (MOCVD) with a carrier concentration of I x 10'''c.
n'-GaAs layer 2 with a thickness of 2 μm and a carrier concentration of 5×10 14 cm−” as a light absorption layer and a thickness of 4 μm.
m of n-GaAs layers 3 are sequentially grown.

(2)  n”−GaAs層3の受光部を残して選択エ
ツチングを行う。
(2) Perform selective etching leaving the light-receiving portion of the n''-GaAs layer 3 intact.

エッチャントは ill□SO* + 8H20□+tut。The etchant is ill□SO*+8H20□+tut.

である。It is.

(31n ’−GaAs Jii 2の受光部とn側ボ
ンディングパッド部を残して選択エツチングを行う。
(Selective etching is performed leaving the light receiving part of 31n'-GaAs Jii 2 and the n-side bonding pad part.

エッチャントは(2)と同じである。The etchant is the same as (2).

(4)  M OCV D法により、高抵抗層(ウィン
ド層)として厚さ3μmのn−Alo、 、Gao、 
Js N 4を成長する。
(4) By MOCVD method, 3 μm thick n-Alo, Gao,
Grow Js N 4.

(5)受光領域のn−Alo、 3Gao、 43層4
を0.5μmの厚さになるまでエツチングする。
(5) n-Alo, 3Gao, 43 layers in the light receiving area 4
is etched to a thickness of 0.5 μm.

(6)n−八lo、 zGao、 q八S層4の表面に
形成した厚さ1500人の5ilN4層6をマスクにし
てZnを拡散してp°型領領域5形成する。
(6) Zn is diffused using the 1500-thick 5ilN4 layer 6 formed on the surface of the n-8lo, zGao, q8S layer 4 as a mask to form the p° type region 5.

なお、SiJ、層6はパッシベーション膜としてそのま
ま残しておく。
Note that the SiJ layer 6 is left as it is as a passivation film.

(7)pe型領領域5内ポンディングパッドを含み、厚
さ1000/1000/2000人のTi/Pt/Au
よりなるn側オーミック電極8を受光部7の周囲に形成
し、n ’−GaAs層2上に厚さ300 / 270
0人のAuGe/Au −よりなるn側オーミック電極
9を形成する。
(7) Ti/Pt/Au with a thickness of 1000/1000/2000 including the bonding pad in the PE type region 5
An n-side ohmic electrode 8 made of
An n-side ohmic electrode 9 made of AuGe/Au - is formed.

第2図は第2の発明によるpinホトダイオードの断面
図である。
FIG. 2 is a sectional view of a pin photodiode according to a second invention.

図において、 Tll  MOCVD法により、5l−GaAs基板1
上に、コンタクト層としてキャリア濃度I X 10”
 cm−’、厚さ2μmのn ’−GaAs層2を成長
する。
In the figure, a 5l-GaAs substrate 1 is prepared by the Tll MOCVD method.
On top, a contact layer with a carrier concentration of I x 10"
An n'-GaAs layer 2 with a thickness of 2 μm and a thickness of 2 μm is grown.

(21n”−GaAs層2の受光部とn側ポンディング
パッド部を残して選択エツチングを行う。
(Selective etching is performed leaving the light receiving part and the n-side bonding pad part of the 21n''-GaAs layer 2.

(3)光吸収層としてキャリア濃度5X1014cm−
’、厚さ4μmのn−GaAs層3と1 高抵抗層(ウィンド層)として厚さ0.5μmのn−^
lo、 3Ga6. Js層4 を順次成長する。
(3) Carrier concentration 5X1014cm- as a light absorption layer
', n-GaAs layers 3 and 1 with a thickness of 4 μm and an n-^ with a thickness of 0.5 μm as a high resistance layer (wind layer)
lo, 3Ga6. Js layer 4 is grown sequentially.

(4)  n−−^L、 :+Gao、 Js層4の表
面に形成されたSi3N4層6をマスクにしてZnを拡
散してp′型領領域5形成する。
(4) n--^L, :+Gao, Using the Si3N4 layer 6 formed on the surface of the Js layer 4 as a mask, Zn is diffused to form a p' type region 5.

なお、5i3Na層6はパッシベーション膜としてその
まま残してお(。
Note that the 5i3Na layer 6 is left as it is as a passivation film (.

(5)  n−−GaAs層3を選択エツチングしてn
側ポンディングパッド形成部のn ”−GaAs層2を
露出させる。
(5) Selectively etching the n--GaAs layer 3 to
The n''-GaAs layer 2 in the side bonding pad forming portion is exposed.

(61p’型領域5内にポンディングパッドを含み、T
i/Pt/Auよりなるn側オーミック電極8を受光部
7の周囲に形成し、n ”−GaAs層2にAuGe/
Auよりなるn側オーミック電極9を形成する。
(including a bonding pad in the 61p' type region 5, T
An n-side ohmic electrode 8 made of i/Pt/Au is formed around the light receiving part 7, and the n''-GaAs layer 2 is made of AuGe/
An n-side ohmic electrode 9 made of Au is formed.

本発明による構造は、いずれもn・−GaAs層2とn
側オーミック電極8の重なりがなくなるため、受光部以
外の不要な容量が減り、pinダイオード全体の容量が
低減できる。
In the structure according to the present invention, both the n·-GaAs layer 2 and the n
Since the side ohmic electrodes 8 do not overlap, unnecessary capacitance other than the light receiving portion is reduced, and the capacitance of the entire pin diode can be reduced.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によるpinダイオー
ドは、容量が低減され、高速応答が可能となる。
As described in detail above, the pin diode according to the present invention has a reduced capacitance and is capable of high-speed response.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は第1の発明によるpinホトダイオードの断面
図、 第2図は第2の発明によるpinホトダイオードの断面
図、 第3図(1)、(2)は従来例によるpinホトダイオ
ードの斜視図、断面図である。 図において、 1は5r−GaAs基板、 2はn ”−GaAs層、 3は光吸収層でn−GaAs Ns 4は高抵抗N(ウィンド層)で n−^l(1,3Ga@、 ?AS層、5はp゛型領領
域 6は5iJa層6. 7は受光部、 8はp側オーミック電極、 9はn側オーミック電極 丁11辺 ’X’2n各トシ旧2爲ヤ^41・力゛ンλゝト。 0釘(a l”El
FIG. 1 is a cross-sectional view of a pin photodiode according to the first invention, FIG. 2 is a cross-sectional view of a pin photodiode according to the second invention, and FIGS. 3 (1) and (2) are perspective views of a conventional pin photodiode. FIG. In the figure, 1 is a 5r-GaAs substrate, 2 is an n''-GaAs layer, 3 is a light absorption layer, n-GaAs Ns, 4 is a high resistance N (wind layer), and n-^l (1,3Ga@, ?AS). 5 is the p-type region 6 is the 5iJa layer 6. 7 is the light receiving part, 8 is the p-side ohmic electrode, 9 is the n-side ohmic electrode.゛ an λ ゝ t.

Claims (2)

【特許請求の範囲】[Claims] (1)基板(1)上に一導電型コンタクト層(2)と、
一導電型光吸収層(3)とを順次成長し、該光吸収層(
3)とコンタクト層(2)を選択的に除去した後、該コ
ンタクト層(2)より抵抗値の高い高抵抗層(4)を成
長し、該光吸収層(3)上の該高抵抗層(4)を他導電
型領域(5)に変換し、一導電型コンタクト層(2)と
他導電型領域(5)上に電極を形成してなることを特徴
とするpinホトダイオード。
(1) a contact layer (2) of one conductivity type on the substrate (1);
A light absorption layer (3) of one conductivity type is grown sequentially, and a light absorption layer (3) of one conductivity type is grown.
After selectively removing 3) and the contact layer (2), a high resistance layer (4) having a higher resistance value than the contact layer (2) is grown, and the high resistance layer (4) on the light absorption layer (3) is grown. A pin photodiode characterized in that (4) is converted into a region (5) of another conductivity type, and electrodes are formed on a contact layer (2) of one conductivity type and a region (5) of another conductivity type.
(2)基板(1)上に一導電型コンタクト層(2)を成
長し、該コンタクト層(2)を選択的に除去した後、光
吸収層(3)と、該コンタクト層(2)より抵抗値の高
い高抵抗層(4)とを成長し、受光領域を含んで選択的
に該高抵抗層(4)を他導電型領域(5)に変換し、一
導電型コンタクト層(2)と他導電型領域(5)上に電
極を形成してなることを特徴とするpinホトダイオー
ド。
(2) After growing a contact layer (2) of one conductivity type on the substrate (1) and selectively removing the contact layer (2), the light absorption layer (3) and the contact layer (2) are grown. A high resistance layer (4) with a high resistance value is grown, the high resistance layer (4) is selectively converted into a region (5) of another conductivity type including the light receiving region, and a contact layer (2) of one conductivity type is grown. A pin photodiode characterized in that an electrode is formed on a region (5) of a different conductivity type.
JP60244418A 1985-10-31 1985-10-31 Pin photo diode Pending JPS62104178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60244418A JPS62104178A (en) 1985-10-31 1985-10-31 Pin photo diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60244418A JPS62104178A (en) 1985-10-31 1985-10-31 Pin photo diode

Publications (1)

Publication Number Publication Date
JPS62104178A true JPS62104178A (en) 1987-05-14

Family

ID=17118366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60244418A Pending JPS62104178A (en) 1985-10-31 1985-10-31 Pin photo diode

Country Status (1)

Country Link
JP (1) JPS62104178A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187984A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Semiconductor device
JP2007288089A (en) * 2006-04-20 2007-11-01 Opnext Japan Inc Optical element and optical module
CN100433341C (en) * 2003-06-13 2008-11-12 浜松光子学株式会社 Semiconductor photoreceptor
CN111653645A (en) * 2020-06-15 2020-09-11 京东方科技集团股份有限公司 Detection panel, manufacturing method thereof and ray detection device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187984A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Semiconductor device
CN100433341C (en) * 2003-06-13 2008-11-12 浜松光子学株式会社 Semiconductor photoreceptor
JP2007288089A (en) * 2006-04-20 2007-11-01 Opnext Japan Inc Optical element and optical module
CN111653645A (en) * 2020-06-15 2020-09-11 京东方科技集团股份有限公司 Detection panel, manufacturing method thereof and ray detection device

Similar Documents

Publication Publication Date Title
JPS62104178A (en) Pin photo diode
Gao et al. In/sub 0.53/Ga/sub 0.47/As MSM photodiodes with transparent CTO Schottky contacts and digital superlattice grading
JPH04286373A (en) Infrared detecting device
JPH0542837B2 (en)
JPS5848479A (en) Semiconductor light detector
JPS6398158A (en) Photodiode
JPS6156469A (en) Semiconducltor photodetector
JPS61289678A (en) Avalanche photo diode
JPS61187363A (en) Optical integrated circuit device
JPH05343731A (en) Photodetector
JP3236650B2 (en) Semiconductor light emitting device
JPH01194476A (en) Semiconductor photodetector
JPS59149070A (en) Photodetector
JPH02114675A (en) Semiconductor light emitting element and manufacture thereof
JPS6259905B2 (en)
RU2676185C1 (en) Shf photo detector manufacturing method
JPS55162223A (en) Semiconductor device and its preparation
JPH04246867A (en) Semiconductor photodetector
JPS6262477B2 (en)
JPH03171678A (en) Formation of electrode of semiconductor device
JPS6316689A (en) Semiconductor device
JPH01162382A (en) Semiconductor photodetector
JPS6064464A (en) Semiconductor device and manufacture thereof
JPS63281479A (en) Semiconductor photodetector
JPH04268771A (en) Semiconductor photodetective element