JPH02117181A - Semiconductor light receiving device - Google Patents

Semiconductor light receiving device

Info

Publication number
JPH02117181A
JPH02117181A JP63271324A JP27132488A JPH02117181A JP H02117181 A JPH02117181 A JP H02117181A JP 63271324 A JP63271324 A JP 63271324A JP 27132488 A JP27132488 A JP 27132488A JP H02117181 A JPH02117181 A JP H02117181A
Authority
JP
Japan
Prior art keywords
area
region
semiconductor layer
substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63271324A
Other languages
Japanese (ja)
Inventor
Tetsuo Shiba
哲夫 芝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63271324A priority Critical patent/JPH02117181A/en
Publication of JPH02117181A publication Critical patent/JPH02117181A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily integrate electrodes of each area with electronic circuits disposed on an insulating substrate by providing a first n-type area and a second p-type area in a semiconductor layer provided on a semiinsulating substrate spaced from each other and providing the electrodes of each area in the same flat plane. CONSTITUTION:An n<+>-type first area 10 disposed on a semiconductor layer 2 is formed as an area which leads to a substrate 9 from the surface of the semiconductor layer 2. Likewise, a second p<+>-type area 11 disposed on the semiconductor layer 2 is formed at a place spaced from the first area as an area which leads to the substrate 9 from the surface of the semiconductor layer 2. An n electrode 12 provided on the first area 10 protrudes on the surface of an insulation film through it. A p electrode 13 provided on the second area 11 passes through the insulation film 5 in the same manner as the n electrode and protrudes on the surface. Since the electrodes 12, 13 of the first and second area 10 and 11 are disposed on the same plane, they can be formed on the substrate 9 on which electronic circuits are mounted and therefore integration with electronic circuits is easy.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はアバランシェ フォトダイオード等の半導体
受光装置の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in semiconductor light receiving devices such as avalanche photodiodes.

〔従来の技術〕[Conventional technology]

第3図は従来のアバランシェ フォトダイオードの概略
構成を示す断面図である。この図において(1)はn”
−GaAs基板、(2はその上面に設けられたn−−G
aAs層、(3)は上記n−GaAs層に形成されたp
+領領域(4)は上記ρ1領域の周囲に形成されたp型
ガードリング領域、(51は上記n−GaAs層の表面
に設けられた絶縁膜、(6)は上記p+領領域設けられ
たp電極で、上記絶縁M (51を貫通してその表面に
突出している。(7)は上記基板の下面に設けられたn
電極、(8)は照射される光である。
FIG. 3 is a sectional view showing the schematic structure of a conventional avalanche photodiode. In this figure, (1) is n”
-GaAs substrate (2 is n--G provided on its top surface)
The aAs layer (3) is the p layer formed on the n-GaAs layer.
The + region (4) is a p-type guard ring region formed around the ρ1 region, (51 is an insulating film provided on the surface of the n-GaAs layer, and (6) is the p+ region provided The p-electrode penetrates the insulation M (51) and protrudes from the surface thereof. (7) is the n-electrode provided on the lower surface of the substrate.
The electrode (8) is the irradiated light.

このような構成において、p電極(6)とn電極■との
間に逆方向電圧を印加し、光電を照射すると、この光(
81は受光部を構成するn−GaAs層(2に吸収され
、電子・正孔対を発生させる0発生した電子。
In such a configuration, when a reverse voltage is applied between the p-electrode (6) and the n-electrode (6) and photoelectric is irradiated, this light (
Reference numeral 81 indicates generated electrons which are absorbed by the n-GaAs layer (2) constituting the light receiving section and generate electron-hole pairs.

正孔はn”−GaAs基板(1)及びn7−GaA5J
Wt(2)内の電、界によって互いに反対方向に走行し
、その結果、光電流として外部に取り出される。外部が
ら両電極間に印加する電圧を増やしていくと、走行する
電子又は正孔は半導体中で十分な加速エネルギーを得て
、フォノンとの散乱過程において新たな電子・正孔対を
発生させる。新たに発生した電子又は正札は再び加速さ
れ、同様の過程により更に新たな電子・正孔対を発生さ
れる、いわゆるアバランシェ増倍が生じ、以後、連鎖反
応的に電子・正孔対が発生する。
Holes are formed on n”-GaAs substrate (1) and n7-GaA5J
The electric field inside Wt(2) causes them to travel in opposite directions, and as a result, they are taken out as photocurrent. When the voltage applied between the two electrodes from the outside is increased, the traveling electrons or holes acquire sufficient acceleration energy in the semiconductor, and generate new electron-hole pairs in the scattering process with phonons. The newly generated electrons or regular bills are accelerated again, and new electron/hole pairs are generated through the same process, so-called avalanche multiplication, and thereafter, electron/hole pairs are generated in a chain reaction. .

この結果、光電流も増倍されて外部に取り出される。な
お、画電極に印加される電圧は、p−n接合の降伏電圧
に近いものであり、従ってp−n接合の曲率が高い領域
においては局部的な接合降伏が生じやすいため、曲率緩
和の目的でガードリング領域(イ)が設けられているも
のである。
As a result, the photocurrent is also multiplied and taken out to the outside. Note that the voltage applied to the picture electrode is close to the breakdown voltage of the p-n junction, and therefore, local junction breakdown is likely to occur in areas with high curvature of the p-n junction, so the purpose of curvature relaxation is A guard ring area (a) is provided.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体受光装置は以上のように構成され、電極が
装置の上面と下面に夫々設けられているため、半絶縁性
の基板上に配設されている電子回路等との集積化が困難
という問題点があった。
Conventional semiconductor photodetectors are constructed as described above, with electrodes provided on the top and bottom surfaces of the device, making it difficult to integrate with electronic circuits, etc. arranged on a semi-insulating substrate. There was a problem.

この発明は上記のような問題点を解消するためになされ
たもので、半絶縁性基板上に配設された電子回路等との
集積化が容易な半導体受光装置を提供しようとするもの
である。
This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor light receiving device that can be easily integrated with electronic circuits etc. arranged on a semi-insulating substrate. .

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体受光装置は、半絶縁性の半導体基
板上に第1導電型の半導体層を設けると共に、上記半導
体層に高濃度の第1導電型の第1領域と、第2導電型の
第2領域とを互いに離隔して設け、上記第1領域及び第
2領域の電極を同一面上に設けるようにしたものである
A semiconductor light receiving device according to the present invention includes a semiconductor layer of a first conductivity type on a semi-insulating semiconductor substrate, and a first region of a highly concentrated first conductivity type and a semiconductor layer of a second conductivity type in the semiconductor layer. The electrodes of the first region and the second region are provided on the same surface.

〔作  用〕[For production]

この発明によれば、第1領域及び第2領域の電極を同一
平面に設けているため電子回路等を配設している半絶縁
性基板上に形成することが可能となり、電子回路等との
集積化も容易となるものである。
According to this invention, since the electrodes of the first region and the second region are provided on the same plane, it is possible to form the electrodes on a semi-insulating substrate on which electronic circuits, etc. are arranged. It also facilitates integration.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。第1
図は実施例の構成を示す断面図で、この図において(9
)は半絶縁性のGaAs基板、(21は上記基板上に設
けられたn−GaAsの半導体層で、照射光6)に対し
て光吸収層及び増倍層として作用するものである。叫は
上記半導体層(aに設けられたn+型の第1領域で、上
記半導体層(2)の表面から上記基板(9)に至る領域
として形成されている。(11)は同じく上記半導体層
(2)に設けられたp+型の第2領域で、上記第1領域
から離隔した箇所で上記半導体層(2)の表面から上記
基板(9)に至る領域として形成されている。(51は
上記半導体層(2)の表面に設けられた絶縁膜、(12
)は上記第1領域叫に設けられたn電極で、上記絶縁膜
(51を貫通してその表面に突出している。(13)は
上記第2領域(11)に設けられたn電極で、上記n電
極と同様に上記絶縁膜(5)を貫通してその表面に突出
している。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view showing the configuration of the embodiment, and in this figure (9
) is a semi-insulating GaAs substrate, and (21 is an n-GaAs semiconductor layer provided on the substrate, which acts as a light absorption layer and a multiplication layer for the irradiated light 6). 1 is an n+ type first region provided in the semiconductor layer (a), and is formed as a region extending from the surface of the semiconductor layer (2) to the substrate (9). (2) is a p+ type second region provided at a location separated from the first region, and is formed as a region extending from the surface of the semiconductor layer (2) to the substrate (9). (51 is An insulating film provided on the surface of the semiconductor layer (2), (12
) is an n-electrode provided in the first region, which penetrates the insulating film (51) and protrudes from the surface thereof. (13) is an n-electrode provided in the second region (11), Like the n-electrode, it penetrates the insulating film (5) and protrudes from the surface thereof.

このような構成においてn電極(12)及びn電極〈1
3)間に逆方向電圧を印加すると、第1領域α■と第2
領域(11)との間で半導体層(2)内に横方向の電界
が形成される。この状態で光(aが照射されると、光θ
は半導体層(2)内で吸収され電子・正孔対を発生する
。印加電圧を十分大きくするとアバランシェ増倍が生じ
、増倍された光電流が外部に取り出されることは上述し
た通りである。
In such a configuration, the n-electrode (12) and the n-electrode <1
3) When a reverse voltage is applied between the first area α■ and the second area
A lateral electric field is formed in the semiconductor layer (2) between the region (11) and the semiconductor layer (2). When light (a) is irradiated in this state, the light θ
is absorbed within the semiconductor layer (2) and generates electron-hole pairs. As described above, when the applied voltage is sufficiently increased, avalanche multiplication occurs, and the multiplied photocurrent is taken out to the outside.

なおこの場合、p−n接合の高曲率部における局部的な
接合降伏が問題となるが、上記実施例では第1領域αω
及び第2領域(11)を半絶縁性の基板(9)内に十分
深く形成し、曲率の高い領域が基板(9)内に形成され
るようにしているため局部的な接合降伏を防止すること
が出来るものである。
In this case, local junction breakdown at the high curvature part of the pn junction becomes a problem, but in the above embodiment, the first region αω
The second region (11) is formed sufficiently deep within the semi-insulating substrate (9) so that a region with high curvature is formed within the substrate (9), thereby preventing local junction breakdown. It is something that can be done.

しかし、このような構成によっても局部的な接合降伏が
生ずる場合には、第2図に示すように基板(9)と半導
体層(2)との間にガードリング層〈14)を設け、第
1領域00)及び第2領域(11)を夫々上記ガードリ
ング/lW (+41に至らしめるようにしてもよい。
However, if local junction breakdown occurs even with such a configuration, a guard ring layer (14) is provided between the substrate (9) and the semiconductor layer (2) as shown in FIG. The first area 00) and the second area (11) may each reach the guard ring /lW (+41).

ガードリング層(14)は禁制帯幅の広いAlGaAs
又は、上記半導体層(2)より更に不純物濃度の低いG
aAs或いはAlGaAsによって構成する。なお、以
上の説明では各層の材料としてGaAs、 AlG5A
sを用いた実施例を挙げたが、これに限られるものでは
なく、他の半導体材料、例えばInP、 InGaAs
P、 InGaAs又はCdTe 、 HgCdTe 
、或いはAlGaSb、 AlGaAsSb等を用いて
も同様の効果を期待し得るものである。
The guard ring layer (14) is made of AlGaAs with a wide forbidden band width.
Alternatively, G having an even lower impurity concentration than the semiconductor layer (2)
It is made of aAs or AlGaAs. In addition, in the above explanation, GaAs, AlG5A are used as materials for each layer.
Examples using s are given, but the invention is not limited to this, and other semiconductor materials such as InP, InGaAs
P, InGaAs or CdTe, HgCdTe
Alternatively, similar effects can be expected by using AlGaSb, AlGaAsSb, or the like.

〔発明の効果〕〔Effect of the invention〕

この発明は以上のように構成され、半絶縁性の基板上に
設けられた半導体層にn型の第1領域とn型の第2領域
とを離隔して設け、各領域の電極を同一平面に設は得る
ようにしているため、半絶縁性の基板上に配設されてい
る電子回路等との集積化が容易になるものである。
The present invention is constructed as described above, in which an n-type first region and an n-type second region are provided separately from each other in a semiconductor layer provided on a semi-insulating substrate, and the electrodes of each region are arranged on the same plane. Since the structure is designed to be easily integrated with electronic circuits and the like disposed on a semi-insulating substrate, it is easy to integrate the device with electronic circuits and the like arranged on a semi-insulating substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す概略断面図、第2図
はこの発明の他の実施例を示す概略断面図、第3図は従
来の半導体受光装置を示す概略断面図である。 図において、(9)は基板、(2)はn”’−GaAs
の半導体層、α〔は第1領域、(11)は第2領域、(
9は絶縁膜、(12)はn電極、(13)はn電極、(
14)はガードリング層である。 なお、図中、同一符号は同−又は相当部分を示す。 第1図 第2図 代理人 弁理士  大 岩 増 雄 /4 : 77−)’リンフ゛4雪 第3図 工事性の表示 昭和63年特許願第271.324号 2発明の名称 半導体受光装置 37市正をする者 $1′トとぴ〕関係 1和T出願人 代表、と 4代理人 う補正の対象 明細書の発明の詳細な説明の欄 6補正の内容 明細書第2ページ第13行に [及び ・・(2)内の」 とあるのを [とP+ GaAs領域(3)の間にががる」 と訂正する。 以上
FIG. 1 is a schematic sectional view showing one embodiment of the present invention, FIG. 2 is a schematic sectional view showing another embodiment of the invention, and FIG. 3 is a schematic sectional view showing a conventional semiconductor light receiving device. In the figure, (9) is the substrate, (2) is n''-GaAs
of the semiconductor layer, α[ is the first region, (11) is the second region, (
9 is an insulating film, (12) is an n-electrode, (13) is an n-electrode, (
14) is a guard ring layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Fig. 1 Fig. 2 Agent Patent Attorney Masuo Oiwa / 4: 77-)'Lymph 4 Snow Fig. 3 Indication of workability 1985 Patent Application No. 271.324 2 Name of the invention Semiconductor photodetector device 37 cities Person(s) making the amendment: $1' Totopi] Related: 1) Representative of the applicant; 4) Detailed explanation of the invention in the specification to be amended; 6) Contents of the amendment; 2nd page, line 13 of the specification; [And... in (2)," is corrected to read, "There is a gap between and the P+ GaAs region (3)."that's all

Claims (1)

【特許請求の範囲】[Claims] 半絶縁性の半導体基板上に設けられ、受光部を構成する
第1導電型の半導体層、この半導体層の表面から上記半
導体基板に至る領域を形成し、上記半導体層よりも高濃
度の第1導電型の第1領域、この第1領域から離隔して
上記半導体層に設けられ、上記半導体層の表面から上記
半導体基板に至る領域を形成する第2導電型の第2領域
、及び上記第1領域並びに第2領域に夫々設けられた抵
抗性電極を備えた半導体受光装置。
A semiconductor layer of a first conductivity type provided on a semi-insulating semiconductor substrate and constituting a light-receiving section; a first region of a conductivity type; a second region of a second conductivity type provided in the semiconductor layer at a distance from the first region and forming a region extending from the surface of the semiconductor layer to the semiconductor substrate; A semiconductor light receiving device including resistive electrodes provided in a region and a second region.
JP63271324A 1988-10-26 1988-10-26 Semiconductor light receiving device Pending JPH02117181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63271324A JPH02117181A (en) 1988-10-26 1988-10-26 Semiconductor light receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63271324A JPH02117181A (en) 1988-10-26 1988-10-26 Semiconductor light receiving device

Publications (1)

Publication Number Publication Date
JPH02117181A true JPH02117181A (en) 1990-05-01

Family

ID=17498467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63271324A Pending JPH02117181A (en) 1988-10-26 1988-10-26 Semiconductor light receiving device

Country Status (1)

Country Link
JP (1) JPH02117181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5880489A (en) * 1995-07-31 1999-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor photodetector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193681A (en) * 1984-05-30 1986-05-12 マツクス−プランク−ゲゼルシヤフト ツ−ル フオエルデルング デ−ル ヴイセンシヤフテン エ−.フアオ. Semiconductor device
JPS6373569A (en) * 1986-09-16 1988-04-04 Fujitsu Ltd Manufacture of semiconductor photodetector

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193681A (en) * 1984-05-30 1986-05-12 マツクス−プランク−ゲゼルシヤフト ツ−ル フオエルデルング デ−ル ヴイセンシヤフテン エ−.フアオ. Semiconductor device
JPS6373569A (en) * 1986-09-16 1988-04-04 Fujitsu Ltd Manufacture of semiconductor photodetector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5880489A (en) * 1995-07-31 1999-03-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor photodetector

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