JPS62188424A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To attain the quick phase pull-in by adopting the constitution that a frequency divider and a loop filter being components of a phase locked loop are subjected to be forced schronization and forced initialization, respectively, in response to a change-over timing of an input signal. CONSTITUTION:An input switching instruction signal (f) is generated at a time ts from an input signal switching instruction circuit 1 and the switching of an input signal is attained before and after the time ts. An input (a) appears as it is at an output (c) of a selection circuit 2 before the time ts and the output phase of a counter 82 of a frequency divider 8 is as shown in waveform (d). A signal (d) goes to a low level at the leading of the signal (c), an output of a phase cmparator 3 drives a loop filter 5 via an amplifier 4 and a filter output (e) at the ideal phase pull-in state is shown in waveform at a period T1. In such a case, the filter output (e) goes to a zero level at T/4 of the period T of the output (d) of the counter 82. Thus, quick frequency and phase pull-in are attained.

Description

TECHNICAL FIELD The present invention relates to a phase synchronization circuit, and more particularly to a phase synchronization circuit configured to be selectively supplied with a plurality of input signals to be phase-locked.

Prior art Generally, between phases! ■Once the phase of the input signal to which the phase should be pulled is established and synchronization is established,
It can be assumed that re-retraction will hardly occur unless the input is interrupted. However, when one signal is sequentially selected from a plurality of input signals to be phase-drawn as time passes due to system requirements, it is necessary to perform a phase-drawing operation for each signal individually, and it is difficult to quickly pull the phase. required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase synchronization circuit capable of quickly performing a phase pull-in operation in response to switching of an input signal.

According to the present invention, there is provided a phase synchronization circuit configured so that a plurality of input signals to be phase-locked are selectively supplied, and the phase synchronization circuit is configured such that a plurality of input signals to be phase-locked are selectively supplied. 1
A) A seven-phase synchronization circuit is obtained, which is characterized in that it is configured to perform forced synchronization of the frequency divider constituting the synchronization loop and forced initialization of the loop filter.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which only one of a plurality of input signals Y) to be phase-introduced is selected in a selection circuit 2 according to information instructed by a selection instruction circuit 1, and a phase comparison is performed. (If necessary, a signal may be supplied to the phase comparator 3 via a frequency divider.)

The output of the phase comparator 3 passes through an amplifier 4 and a loop filter 5, then a zero potential supply circuit 6, and is then input to a VCO (voltage controlled oscillator) 7. The output of the VCO 7 is frequency-divided by a frequency divider 8 and becomes the input of the phase comparator 3. Zero potential supply circuit 6 and frequency division 2! i8 is controlled by the control circuit 9 only immediately after the selection instruction circuit 1 switches the input signal.

Before explaining the operation of the embodiment of the present invention in such a configuration, preconditions will be described. First, it is assumed that the nominal repetition frequency of all input signals substantially matches the natural oscillation frequency when the control input of the VCO 7 is set to zero. Next, it is assumed that the phase relationship between both inputs of the phase comparator 3 after a sufficient period of time has elapsed after the phase pull-in for an arbitrary input signal is such that the phases are shifted by 180 degrees from each other as shown in FIG. Furthermore, the frequency division ratio of the frequency divider 8 (if the input signal is input to the comparator via the frequency divider, that frequency divider) is set to be sufficiently large, so that the 5 signals to be compared are repeated. It is assumed that the frequency is several tens of Hz to several H2.

Fig. 3 shows a specific example of the circuit shown in Fig. 1, and Fig. 4 shows the first year time chart of the circuit shown in Fig. 3.

4A to 4A to 4C respectively show the waveforms of the signals a-1 of each part of the circuit of FIG. 3, respectively. In FIG. 4, a and b indicate two of a plurality of input signals, and a state in which the phase synchronization circuit is switched from the state (T1) in which it is synchronized with the input signal a to the input signal The case where the transition to (T2) is shown is shown.

An input switching instruction signal f is generated from the input signal switching instruction circuit 1 at time ts, and input signals are switched before and after that. Before time ts, the input a appears as it is at the output C of the selection circuit 2, and the output phase of the counter 82 constituting the divider 8 has a waveform as shown in FIG. 4d.

What should be noted here is that the signal d transitions to a low level when the signal C rises. The output of the phase comparator 3 drives a loop filter 5 via an amplifier 4 which performs a DC potential shift. Therefore, the filter output e when the ideal phase pull-in state is entered has a waveform as shown in the period T1. At this time, the filter output e becomes zero level at 1/4 of the period T of the output d of the counter 82. The output phase of the counter 82 is constantly monitored by the decoder 81, and the decoder 81
Pulse J is output at every 4 timings.

Next, when the input switching instruction signal f is generated, the input selection signal q instructs the input signal I. Period T2 of selection circuit 2
The output C at is outputted as is, although it is an input. The control circuit 9 detects the time tu when the signal C rises for the first time immediately after the manual switching.
is found, and a reset pulse 1 is generated at this timing tU to bring the counter 82 into a zero phase state. This function is provided by the D type flip 70 knob 91. as shown in the figure. It can be realized in the cylinder by the delay circuit 92 and the AND circuit 93.

Next, the control circuit 9 outputs the counter output d starting immediately after time tu.
A reset pulse 1 is generated at time tv when the phase becomes π/4, thereby controlling the zero potential supply circuit 6 so that the filter output e becomes zero potential.

The time tv is between the reset pulse 1 and the rise time of the counter output d after this time, and is historically specified by the pulse j. A circuit for obtaining reset pulse 1 from pulses i and j can be easily realized using a D-type flip-flop 94 and an AND circuit 95 as shown.

The zero potential supply circuit 6 is realized by a switching circuit such as a relay circuit or a transistor.

In this way, in the interval [3 after time tv, both the frequency and phase pull-in are completed for (g), and all that remains is for the loop of the synchronization circuit to find its own optimal pull-in phase. become.

Note that the phase comparator 3 includes a delay circuit 31. It is composed of an AND gate 32 and a D type flip-flop 33.

Effects of the Invention According to the present invention, by knowing what internal state the steady state of the phase synchronization circuit exhibits and forcibly bringing it into the steady state of phase pull-in after a transient switching of the input signal, the frequency can be quickly adjusted. This has the effect of enabling pull-in and phase pull-in.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the phase relationship between two human input signals of the phase comparator 3 of FIG. 1, and FIG.
The figure shows an example of the shell body of the block in Figure 1, and Figure 4 shows the shell of the block in Figure 3.
3 is a timing chart showing operation waveforms of each part of the circuit shown in the figure. Explanation of symbols of main parts

Claims (1)

[Claims] A phase synchronization circuit configured so that a plurality of input signals to be phase-locked are selectively supplied, wherein the frequency divider forming the phase synchronization loop is forced in response to switching timing of the input signals. A phase synchronization circuit configured to perform synchronization and forced initialization of a loop filter.