JPH08237123A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: To reduce a circuit scale of the phase locked loop circuit inputting an intermittent burst signal. CONSTITUTION: When an input burst signal 1 inputted by the circuit is interrupted, AND gates 12a, 12b inhibit input of two compared signals to a phase comparator. Then a phase difference signal equivalent to that outputted when the phase difference of the compared signals is zero is given to a voltage controlled oscillator 5. Since a semiconductor gate circuit is employeds, large scale circuit integration of this circuit is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit, and more particularly to a phase synchronization circuit for achieving phase synchronization between an output signal of its own circuit and a burst input signal.

[0002]

2. Description of the Related Art A burst signal such as a horizontal synchronizing signal (frequency: 15 KHz) or a vertical synchronizing signal (frequency: 60 Hz) of a television signal has a signal existing period and a signal missing period periodically. The phase locked loop circuit which outputs an output signal synchronized with a burst signal in which the signal existing period and the signal missing period are periodically present has the configuration shown in FIG.

That is, the conventional phase locked loop circuit, as shown in FIG. 1, compares the input burst signal with the frequency division output signal 8 and outputs the phase detection output 9.
And an LPF (Low Pass Filter) 4 for integrating the phase detection output 9 and outputting an integrated output voltage, and holding / non-holding the integrated output voltage by a control signal 2
A sample and hold circuit 7 that outputs 0 and a control voltage 10
The voltage-controlled oscillator 5 which controls the oscillation output frequency and outputs the output signal 11, and the frequency divider 6 which divides the output signal 11 at a predetermined frequency division ratio.

Next, the operation of such a circuit will be described. When the input burst signal 1 is in the signal existing period, the input burst signal 1 and the output signal 11 output from the voltage controlled oscillator 5
The frequency-divided output signal 8 obtained by dividing the frequency is divided by the frequency divider 6 is compared by the phase comparator 3. The phase detection output 9 output according to the comparison result of the phase comparator 3 is integrated by the LPF and input to the sample hold circuit 7.

The sample-hold circuit 7 is brought into the non-holding state by the control signal 2 and outputs the input phase detection output 9 as the control signal 10. The voltage controlled oscillator 5 has its oscillation output frequency controlled by the control signal 10 and outputs an output signal 11 phase-locked with the input burst signal.

In short, the well-known PL
L (Phase Locked Loop) is formed.

On the other hand, when the input burst signal 1 is in the signal missing period, the sample hold circuit 7 is held by the control signal 2 and the held phase detection output 9 is output as the control signal 10. Therefore, if the voltage controlled oscillator 5 is an ideal voltage controlled oscillator, the output signal 11 thereof is held in the phase locked state before being held by the sample hold circuit 7. However, in a realistic voltage-controlled oscillator, the oscillation frequency drifts due to temperature changes and changes over time, so the phase state gradually changes according to the free-running frequency stability due to the unique characteristics of the oscillator used in the circuit. It will be.

By the way, Japanese Patent Laid-Open No. 1-147921 discloses a technique for reducing the synchronization pull-in time by eliminating the initial phase difference in the phase comparator in the PLL. This is a configuration in which an initial phase synchronization circuit is provided, and signals having the same initial phase are input to the phase comparator by simultaneously turning on the switches by the gate circuit.

[0009]

In the above-mentioned conventional phase locked loop circuit, the sample hold circuit is complicated and is composed of an analog circuit, so that the circuit scale is large. In addition, there is a drawback that it is difficult to make an LSI.

Further, the technique disclosed in the above-mentioned patent publication is a technique for shortening the synchronization pull-in time, the circuit scale becomes large, and it is difficult to form an LSI.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a phase locked loop circuit which has a small circuit scale and can be easily integrated into an LSI.

[0012]

A phase synchronization circuit according to the present invention includes a phase comparison means for transmitting a phase difference signal having a value corresponding to a phase difference between two input signals to be compared, and a phase comparison signal for the phase difference signal. A phase-locked loop circuit including an oscillating means for outputting a corresponding oscillating output, which is output when the value of the phase difference between the compared signals is zero when the input signal input to the own circuit is in the disconnection state. A phase difference signal equivalent to the phase difference signal to be input to the oscillating means.

[0013]

By controlling the logic gate circuit with the control signal and suppressing or switching the input signal to the phase comparator, the value of the phase difference between the compared signals when the input signal input to the own circuit is in the disconnection state. A phase difference signal equivalent to the phase difference signal output when is zero is input to the oscillating means.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a phase locked loop according to the present invention, and the same parts as those in FIG. 4 are designated by the same reference numerals.

Unlike the case of FIG. 4, the phase locked loop circuit of the present embodiment disconnects the signal input to the two inputs of the phase comparator 3 during the signal missing period. By doing so, the phase difference signal equivalent to the phase difference signal output when the value of the phase difference is zero is input to the oscillator 5 during the signal missing period.

The configuration will be specifically described below.

In this embodiment, unlike the case of FIG. 4, an AND gate 12a is provided at the reference side input of the phase synchronizer 3 and an AND gate 12b is provided at the comparison side input. For this reason,
When the control signal 2 is at the high level, the input burst signal 1 becomes the input signal 121 to the phase synchronizer 3 via the AND gate 12a, and the divided output signal 8 becomes the AND gate 12.
It becomes the input signal 122 to the phase synchronizer 3 via b. Therefore, when the control signal 2 is at the high level, the well-known P
LL is formed.

That is, the phase comparator 3 compares the input burst signal 1 with the frequency-divided output signal 8 and outputs a phase detection output 9 having a value corresponding to the phase difference between the two signals. The LPF 4 integrates the phase detection output 9 and outputs a control voltage 10. The voltage controlled oscillator 5 controls the oscillation output frequency with the control voltage 10 and outputs the output signal 11. The frequency divider 6 outputs the output signal 1
1 is divided by a predetermined dividing ratio, and a divided output signal 8 is output. The time constant of the LPF 4 is sufficiently larger than the signal missing period.

On the other hand, when the control signal 2 is at the low level, the AND gates 12a and 12b perform the output inhibition control of the input burst signal 1 and the frequency division output signal 8. That is,
By setting the control signal 2 to the low level during the signal missing period, the signal input to the two inputs of the phase comparator 3 is cut off. As a result, during the signal loss period, the phase difference signal equivalent to the phase difference signal output when the phase difference is zero is input to the oscillator 5.
Therefore, even if an intermittent burst signal is input, each gate is digitally controlled by the control signal, so that the function equivalent to that of the conventional sample hold circuit (see FIG. 4) can be realized with a small scale circuit.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. FIG. 2 is a time chart showing the operation of each part of the phase locked loop circuit of FIG.
, Divided output signal 11, control signal 2, and phase comparator 3
Input signals 121 and 122 are shown.

In the figure, since the control signal 2 is at a high level when the input burst signal 1 is in the signal existing period, both the AND gates 12a and 12b are in the non-inhibited control state (inhibition release state). Therefore, the divided output signal is input to the phase comparator 3 as the input signal 121, and the input burst signal is input to the phase comparator 3 as the input signal 122.

In the phase comparator 3, the phases of these two signals 121 and 122 are compared, and the phase detection output 9 output according to the comparison result is integrated by the LPF 4 to obtain the control voltage 1
It is output as 0. The voltage controlled oscillator 5 has a control signal 10
The oscillation output frequency is controlled by and the output signal 11 phase-locked with the input burst signal 1 is output.

On the other hand, when the input burst signal 1 is in the signal missing period, the AND gate 12a is controlled by the control of the control signal 2.
Both 12 and 12b are in the inhibition control state (inhibition state). Therefore, the input signals 121 and 122 are not transmitted, and the input burst signal 1 and the divided output signal 8 are not input to the phase comparator 3.

Therefore, the comparison result of the phase comparator 3 becomes the same as the synchronized state (state where the phase difference is zero), no phase error is detected, and the LPF 4 holds the time constant. Therefore, if the voltage controlled oscillator 3 is an ideal voltage controlled oscillator, its output signal 11 is held in the phase locked state before being inhibited by the AND gates 12a and 12b.

However, in a realistic voltage controlled oscillator, even if the control voltage 10 is constant, the oscillation frequency drifts due to temperature changes and changes over time. Therefore, the phase state gradually changes according to the free-running frequency stability due to the unique characteristics of the oscillator used in the circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. 3, the same parts as those in FIGS. 1 and 4 are indicated by the same reference numerals.

In the present embodiment, unlike the case of FIG. 1, the same signal is input to the two inputs of the phase comparator 3 during the signal missing period. By doing so, a phase difference signal equivalent to the phase difference signal output when the phase difference is zero is input to the oscillator 5, as in the case of the first embodiment.

The configuration will be specifically described below.

In the figure, AND gates 12a and 12
b and the OR gate 13 form a selection circuit.
That is, while the control signal 2 is directly input to the AND gate 12a, the control signal 2 is input to the AND gate 12b after being inverted by the inverter 14. Therefore, when the control signal 2 is low level, the frequency division output signal 8 is input to the phase comparator 3 through the AND gate 12b and the OR gate 13, and when the control signal 2 is high level, the input burst signal 1 is the AND gate 12a and It is input to the phase comparator 3 via the OR gate 13.

In short, the input burst signal 1 and the output signal 8 of the frequency divider 6 are selectively input to the phase comparator 3 by digital control of the control signal 2 by the logical level.

Therefore, when the control signal 2 is at a low level, a well-known PLL is formed. That is, the phase comparator 3 compares the phases of the input burst signal 1 and the frequency-divided output signal 8 and outputs the phase detection output 9. The LPF 4 integrates the phase detection output 9 and outputs a control voltage 10. The voltage controlled oscillator 5 controls the oscillation output frequency with the control voltage 10,
The output signal 11 is output. The frequency divider 6 is the voltage controlled oscillator 5
Output signal 11 is divided by a predetermined dividing ratio, and a divided output signal 8 is output. The time constant of the LPF 4 is sufficiently larger than the signal missing period.

In such a configuration, the input burst signal 1
Is in the signal existence period, the ON control of the control signal 2 causes the AND gates 12a and 12b and the OR gate 1 to operate.
The selection circuit according to 3 selects the input burst signal 1.
Then, the selected input burst signal 1 and the frequency-divided output signal 8 are input to the phase comparator 3, and the phase comparator 3
The phases are compared at. The phase detection output 9 output according to the comparison result of the phase comparator 3 is integrated by the LPF 4 and output as a control voltage. The voltage controlled oscillator 5 has its oscillation frequency controlled by a control signal 10 and outputs an output signal 11 phase-locked with the input burst signal.

On the other hand, when the input burst signal 1 is in the signal missing period, the AND gate 1 is turned off by the control signal 2 being turned off.
The selection circuit composed of 2a and 12b and the OR gate 13 selects the divided output signal 8. Then, the phase comparator 3
2 inputs, that is, both the reference side input and the comparison side input,
The divided output signal 8 is input.

Since this state is the same as the phase locked state, the comparison result of the phase comparator 3 is the same as the synchronized state (state where the phase difference is zero), so no phase error is detected and the LP
It is held at F4 for the time constant. Therefore, if the voltage controlled oscillator 3 is an ideal voltage controlled oscillator, its output signal 1
1 is AND gates 12a and 12b and OR gate 1
The phase locked state before being selected by the selection circuit according to No. 3 is held.

However, in a practical voltage controlled oscillator, even if the control voltage 10 is constant, the oscillation frequency drifts due to temperature changes and changes over time. Therefore, the phase state gradually changes according to the free-running frequency stability due to the unique characteristics of the oscillator used in the circuit.

As described above, the first embodiment or the second embodiment
If the phase-locked loop circuit is constructed as in the above embodiment, the construction becomes simpler than the conventional circuit. Since the AND gates 12a and 12b and the OR gate 13 can be configured by semiconductor logic gate circuits instead of analog circuits,
It is easy to make LSI.

It is obvious that the phase locked loop circuit of this embodiment can also be used for receiving burst signals and radio signals other than television signals.

If the input burst signal 1 is a signal that is periodically input like a television signal, the logic level of the control signal 2 can be easily changed according to the signal existing period and the signal missing period. When the signal is not a cyclically input signal, the control signal 2 may be created using a monostable multivibrator or the like that outputs a pulse according to the rising timing of the input burst signal 1.

[0040]

As described above, according to the present invention, even if an intermittent burst signal is input, a phase difference signal equivalent to the phase difference signal output when the phase difference is zero is sent to the voltage controlled oscillator. By controlling so as to input, there is an effect that the circuit scale can be reduced and LSI can be easily made.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of each part of the phase locked loop circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a phase locked loop circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

 1 input burst signal 2 control signal 3 phase comparator 4 LPF 5 voltage controlled oscillator 6 frequency divider 12a, 12b AND gate 13 OR gate 14 inverter

Claims (4)

[Claims] 1. A phase comparison means for transmitting a phase difference signal having a value corresponding to a phase difference between two inputted compared signals.
A phase synchronization circuit including an oscillating means for transmitting an oscillation output according to the phase difference signal, wherein the value of the phase difference between the compared signals is zero when the input signal input to the own circuit is in a disconnection state. And a phase difference signal equivalent to the phase difference signal output when the input signal is input to the oscillating means. 2. The phase locked loop circuit according to claim 1, wherein the input control means inhibits the input of the two compared signals to the phase comparison means when the input signals are in a disconnected state. 3. The phase synchronization circuit according to claim 1, wherein the input control means inputs the oscillation output to the phase comparison means as the two compared signals when the input signal is in a disconnection state. . 4. The phase locked loop circuit according to claim 2, wherein the input control means is composed of a semiconductor gate circuit.