JPS63245088A - Automatic phase control circuit - Google Patents

Abstract

PURPOSE:To allow two timings to coincide with each other in a simple constitution, by switching the phase of a reference signal at the detection timing of a phase switching timing detection means when the polarity of the pulse outputted from the phase switching timing detection means is switched three or more times continuously. CONSTITUTION:A switching timing 11 of the phase of an input signal and a switching timing 16 of the phase of the reference signal are detected by an ID detector 20 interruptedly in accordance with their switching periods, and the pulse having the same polarity is outputted if both timings coincide with each other, and the pulse having the opposite polarity is outputted if they do not coincide with each other. If the polarity of this pulse is changed at least three times continuously, the phase of the reference signal is forcibly switched by a switch control circuit 21. Thus, the phase switching timing of the input signal and that of the reference signal are allowed to coincide with each other by the simple constitution where the change of the polarity of the pulse is decided only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an automatic phase control circuit (hereinafter referred to as an APC circuit).

(Prior Art) In a video tape recorder (hereinafter referred to as VTR), a color signal is recorded after being converted to a low frequency, and during reproduction, it is returned to the original frequency by inverse conversion.

Conventionally, this frequency conversion has been performed by an automatic phase control circuit (hereinafter referred to as an APC circuit) as shown in FIG. For example, in the case of PAL system, the reproduced 626k
The frequency of the Hz chroma signal is converted by the frequency converter 11 and returned to a signal having the original frequency of 4.43 MHz. This converted output is input to the phase detector 12, and its phase is compared with the output of the 4.43MH2 crystal oscillator 13, which serves as a reference. The reproduced chroma signal is synchronized with the output of the crystal oscillator 13 by controlling the variable oscillator 14 using this phase comparison output to change the frequency of the carrier CW of the frequency converter 11.

Roughly speaking, in the APC circuit of FIG. 6, in order to speed up the convergence, the phase of the output of the crystal oscillator 13 is changed by the phase shifter 16.
This and the reproduced chroma signal are monitored by the burst ID detector 17, and if the phase difference between the two (O'''' in the synchronous state) is close to 180'', the phase of the carrier CW is shifted by a phase inverter. It is designed to be reversed at 15.

By the way, in the chroma signal of the PAL system, the phase of the color burst signal is one horizontal scanning period fl! (hereinafter referred to as 1H), the angle is alternately switched between +45° and -45°, so it is necessary to increase the filter characteristics of the phase detector 12.

However, doing so slows down the response of the APC circuit.

To solve this problem, the phase of the reference signal is 90
It is conceivable to prepare two different signals and alternately switch between them every day.

By doing this, APC with a phase difference of 0'' can be applied to the color burst signals of +45° and -45°, so that the above problem can be solved.

However, in this case, the phase of the color burst signal (+45
°, -45) switching timing and the reference signal phase (
It is necessary to have a configuration that matches the switching timings of +45° and -45°, and the problem is how to easily realize this.

As described above, in conventional APC circuits that convert the frequency of PAL chroma signals using two reference signals, the timing of switching the phase of the color burst signal and the timing of switching the phase of the reference signal have conventionally been matched. There was a desire to realize a simple configuration for this purpose.

Therefore, an object of the present invention is to provide an APC circuit that can match the above two timings with a simple configuration.

, [Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for changing the phase switching timing of an input signal (for example, a color burst signal) and the phase switching timing of a reference signal. Detection is performed intermittently according to these switching cycles, and if the timings match, a pulse of the same polarity is output, and if they do not match, a pulse of the opposite polarity is output, and the polarity of this pulse is at least 3. If the reference signal changes continuously, the phase of the reference signal is forcibly switched.

(Function) According to the above configuration, the phase switching timing of the input signal and the phase switching timing of the reference signal can be matched with each other with a simple configuration that only determines the change in the polarity of the pulse.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment.

In FIG. 1, the same parts as in FIG. 6 are given the same reference numerals.

In FIG. 1, 18 is a crystal oscillator that generates two reference signals having a phase difference of 90'' from each other.

19 is the above two reference signals under one horizontal scanning period W4<a,
This is a switch circuit selected by 1H).

20 is an ID detection circuit that detects the phase switching timing between the reference signal outputted from the phase shifter 116 and the reproduced chroma signal outputted from the frequency converter 11 during the color burst period. The detection output of this IO detection circuit 20 is 1H
This is a pulse per pulse.

When the above two switching timings match, the polarity of this pulse is set to be always positive, for example. On the other hand, when the switching timings do not match, the polarity of the pulse is set to repeat positive and negative every 1H. That is, as shown in FIG. 2, when the color burst signal B and the reference signal @SR have the same polarity, a pulse of positive polarity is obtained every day. On the other hand, when the color burst signal Bu and the reference signal SR have opposite polarities, as shown in FIG.
Positive polarity pulses and negative polarity pulses are alternately obtained every IH'.

The ID detection circuit 20 further detects the above positive polarity pulse as
slice it with
to obtain RefID pulses.

The switch control circuit 21 looks at the output status of these two pulses, determines the polarity relationship between the color burst signal Bυ and the reference signal SR, and if they are the same polarity, maintains the current switching timing of the switch circuit 19, If the polarity is opposite, the phase of the reference signal S3 is forcibly switched.

FIG. 4 is a circuit diagram showing a specific configuration of the switching circuit 21. As shown in FIG. In the figure, 5RFF1 to 5RFF4 are SR flip-flop circuits, DFF1 to DFF2 are D flip-flop circuits, TFF1 and 7FF2 are T flip-flop circuits, 01 to G10 are AND gates, and G11 is an OR gate. , 11.12 are inverters.

The operation of this switching circuit 21 will be explained with reference to FIG. In FIG. 5, when the ID pulse is output from the ID detection circuit 20, the SR flip-flop circuit 5RFF
1 is set, and its Q output becomes high level. This Q output is a horizontally periodic iH pulse (see Figure 5).
At the rising edge of DF, the D flip-flop circuit DF
It is latched to F1. As a result, the Q output of this D flip flow circuit DFF1 becomes high level, and this Q
The output of the AND gate G3, which receives the output and the Q output of the SR flip 70 tube circuit 5RFF1, becomes high level at the next burst gate timing. When the RerIQ pulse comes at this burst gate timing, the SR flip-flop circuit 5RFF3 is set and its Q output becomes high level. This SR flip 70 tube circuit 5
The Q output of RFF3 is delayed by a D flip-flop circuit DFF2 using the fH pulse as a clock. As a result, when the SR flip-flop circuit 5RFF1 is set by the ID pulse output in the next burst gate period, the output of the AND gate G8 becomes high level, and the SR flip-flop circuit 5RFF4 is set. While the Q output of this frill rough 0-tube circuit 5RFF4 is at a high level, the SR flip 70-tube circuit 5RFF3
When the Q output switches from low level to high level again, AND gate G10 is activated by a burst gate pulse (BG
pulse) passes. This BG pulse, together with the f and 4 pulses, is supplied to the T flip flow circuit TFF2 through the OR gate G11. As a result, the output polarity of the T flip-flop circuit TFF2, which had been inverted in 1H cycles by the fl and I pulses, is forcibly inverted by the BG pulse, and the phase switching timing of the reference signal SR is changed to the phase of the color burst signal B. The switching timing can be matched.

In this way, in the circuit shown in Figure 4, an ID pulse is output and the 1H
Later the RafID pulse comes out and the next 18! The phase of the reference signal SR is switched during the period of the color burst signal Bu only when there is a pulse output pattern in which 10 pulses are output at 1H and a RefID pulse is output after the next 1H.

Incidentally, if the 2H pulse is not a ReflD pulse but a 10 pulse, carrier inversion is performed.

As described above, in this embodiment, the color burst signal B
The phase switching timing of u and the phase switching timing of the reference signal SR are detected intermittently every color burst period, and if the two timings match, a pulse of the same polarity is output, and if they do not match, a pulse of the same polarity is output. A pulse of opposite polarity is output, and when the polarity of this pulse changes three times in succession, the phase of the reference signal SR is forcibly switched.

Therefore, according to this embodiment, the timing of changing the phase of the color burst signal Bu and the timing of changing the phase of the reference signal SR can be made to coincide with the timing of changing the phase of the color burst signal Bu with a simple configuration that only determines the change in the polarity of the pulse.

In the above explanation, the present invention is applied to an APC circuit used for frequency conversion of color signals, but it goes without saying that the present invention can also be applied to other APC circuits. be.

(Effects of the Invention) As described above, according to the present invention, the polarity switching timings of the color burst signal and the reference signal can be matched with each other with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
3 and 3 are diagrams for explaining the operation of FIG. 1, and FIG.
The figure is a circuit diagram showing an example of a specific configuration of the switching circuit shown in Figure 1, Figure 5 is a timing chart for explaining the operation of the tJ44 diagram, and Figure 6 is a circuit diagram showing the configuration of a conventional APC circuit. It is. 11... Frequency conversion circuit, 12... Phase detection circuit,
14... ■C0115... Phase inversion circuit, 16...
・Phase shift circuit, 18...Crystal oscillator, 19...
□Switch circuit, 20...-IO detection circuit, 21...
switching circuit. Applicant's agent Patent attorney Takehiko Suzue 2n◆1H Figure 2 2n◆1H Figure 3

Claims (1)

[Scope of Claims] Phase detection means for phase-detecting an input signal whose two phases alternately switch at a predetermined cycle and a reference signal whose two phases alternately switch at the predetermined cycle; an oscillation means whose oscillation output phase is controlled by a detection output of the oscillator; and oscillation means that intermittently detects the phase switching timing between the input signal and the reference signal at the predetermined period, and the phase of the input signal and the reference signal. When the switching timings match, a pulse with the same polarity is output as the detection output,
If they do not match, the phase switching timing detection means alternately outputs pulses of opposite polarity, and when the polarity of the pulse output from this phase switching timing detection means switches three or more times in succession, the An automatic phase control circuit comprising: phase switching means for switching the phase of the reference signal at the detection timing of the phase switching timing detection means;