JPH0341892A - Automatic phase control circuit - Google Patents

Abstract

PURPOSE:To attain high speed system synchronization by deciding the system phase synchronization to a burst signal so as to control the phase of the synchronization switching. CONSTITUTION:A phase detector 22 compares the phase of a burst signal from a terminal 21 with an output of a switch 24 to apply phase control of a crystal voltage controlled oscillator VXO 23 based on a phase error output to obtain two carriers whose phase differs by 90 deg.. The switch 24 switches two carriers alternately and the switch 25 switches the two carriers alternately in the opposite phase to the case with the switch 24. An ID detector 26 compares the phase of the output of the switch 25 with the phase of the burst signal and gives a phase detection output to a switch 27. The switch 27 selects the phase detection output alternately and a control circuit 28 decides the output of the switch 27 logically to control the switching phase of switches 24, 25, 27 so that the system reaches the normal state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an automatic phase control circuit used when processing a PAL television signal.

(Prior art) In a PAL television signal, the burst signal included in the color signal alternates in phase by +45° -45@ in one horizontal period, based on the (B-Y) axis of the color difference signal. is sent repeatedly. Television receivers generate a color carrier wave (carrier) to perform color demodulation, and an automatic phase control circuit that forms an automatic phase lock loop is used to lock the phase of this carrier to the burst signal. It is being

FIG. 9 shows a conventional automatic phase control circuit.

A color signal (burst signal) is supplied to the input terminal 11,
The signal is supplied to a phase detector 12 and an ID detector 16.

Reference numeral 13 denotes a voltage controlled oscillator, which generates two carriers R1 and R2 having a phase difference of approximately 90''. These carriers R1 and R2 are supplied to a switch 14. The output of this switch 14 is input to the phase detector 12 via a 90'' phase shifter 15. Therefore, the phase detector 12 performs phase detection of the burst signal and the output from the 90'' phase shifter 15, and supplies the phase error output to the phase control terminal of the voltage controlled oscillator 13 via a filter.

Furthermore, the output of switch 14 is also supplied to ID detector 16 . This ID detector 16 performs phase detection of the human input burst signal and the output from the switch 14 every horizontal period, and outputs each detection output to the first and second output terminals. The signals (pulses) output to the first and second output terminals are input to the control circuit 17. The control circuit 17 includes the ID detector 1
If pulses are obtained only from the first output of 6, then
It is determined to be normal and the current switching phase of the switch 14 is maintained. However, if pulses are obtained alternately from the first and second output parts, it is determined that there is an abnormality (reverse phase) and the switch 1
Reverse the switching phase of 4.

The phase detector 12 derives an output with no constant change when the phase difference of the re-input signals differs by 90', and when the phase difference of the re-input signals deviates from 90', outputs an output corresponding to the deviation. The same goes for the ID detector 16. Therefore, if the switching phase of the switch 14 and the phase of the incoming burst signal are in the same phase, a constant DC output is obtained from the phase detector 12, and the ID The maximum output is obtained from the detector 16 each time a burst signal arrives.

FIG. 10 is an explanatory diagram showing the operation of the above circuit. now,
It is assumed that the phase relationship is normal as shown in FIG. 10(A). CBI and CB2 are burst signals that differ in phase by 90'' and arrive alternately every horizontal period. In this case,
A constant detection output is obtained from the phase detector 12, but I
Every time a burst signal arrives from the D detector 16,
A pulse waveform as shown in FIG. 10(B) is obtained as IDI. Further, no pulses are obtained from the second output section of the ID detector 16.

Assume that the switching phase of the switch 14 is reversed for some reason. Then, as shown in FIG. 11(A), the phase of carrier R2 is compared with the burst signal CBI, and
The phase of carrier R1 is compared with burst signal CB2. Then, as shown in FIG. 11(B), the ID detector 16 initially obtains a detection output with a low level because the phase difference is close to 90". On the other hand, in the loop on the voltage-controlled oscillator 13 side, , attempts to pull in the phase, so that the phase of carriers R1 and R2 is gradually controlled to the phase position shown in FIG. 11(C).Then, as shown in FIG. 11(D), , the detection output can now be obtained from the ID detector 16, and the detection output (positive) (IDI) of the burst signal CBI and carrier R2 (the same figure (E
)), and the detection output (negative) (In)2) of the burst signal CB2 and carrier R1 (FIG. 2(F)) can be obtained at high levels. As a result, the control circuit 17 determines that the switching phase of the switch 14 is the opposite phase, and inverts the phase of the switch 14. Therefore, the system becomes in a normal phase state and obtains a carrier phase-synchronized with the burst signal.

(Problems to be Solved by the Invention) According to the conventional phase control circuit described above, when the timing of the switch is reversed due to some disturbance from the normal phase synchronization state, an ID detection output indicating the state is immediately obtained. First, it takes time. For this purpose, switch 14
There is a problem in that the hue is disturbed until the eyes are switched to a normal state. Furthermore, there is a problem with special playback in the long-term (LP) mode of a VTR (video tape recorder). Normally, the phase of the burst signal would be +45'-45a and would arrive repeatedly every 1H, but in the case of special playback, this repetition is not necessarily continuous. This is because the tracks are not scanned continuously and may be reproduced by skipping tracks. For this reason, the phase of the burst signal is now +45'
-45', another expensive detector is required.

Therefore, in the present invention, the detection output of the ID detector is obtained by repeating positive and negative pulses for each IH in the normal phase lock state, and when the level of the detection output of the ID detector becomes small, the detection output of the ID detector is The automatic phase control circuit has a means for obtaining a detection output by switching the phase of the manually input signal of the detector, and is capable of determining the state of the system phase based on this detection output, and is capable of obtaining system synchronization at high speed. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a voltage controlled oscillator that obtains a first carrier, a second carrier having a phase difference of approximately 90'' from the first carrier, and a first switch that alternately switches and derives the first and second carriers at a period of , and a first switch that alternately switches the first and second carriers at a predetermined period and in opposite phase to the first switch; a second switch derived by
Comparing the phase of the burst signal that arrives with the phase alternately switching by approximately 90@ in the predetermined period and the output of the first switch, and controlling the phase of the voltage controlled oscillator based on the phase error output. a first phase detector, a second phase detector that compares the phases of the output of the second switch and the burst signal, and outputs a phase detection output to the first and second output sections at the predetermined period; a third phase detector that alternately selects phase detection outputs of the first and second output sections of the second phase detector at the predetermined period and outputs them to the first and second output sections, respectively; a control circuit that determines the logic content of the switch and the first and second output parts of the third switch and controls the phase of the synchronous switching operation of the first to third switches to be fixed or reversed. It is equipped with the following.

(Operation) By the above means, the first and second carriers having a phase difference of 90' from each other are made to correspond to the burst signal having a phase difference of 90'. The relationship is 9 for the burst signal of one phase.
Set the relationship between 0'' and 180''. As a result, under normal conditions when the system is synchronized to the burst signal, positive and negative detection outputs are obtained alternately from the ID detection section for each IH, but in an asynchronous state, there is no detection output, or only one (positive and negative) detection output is obtained. or negative) is the only detected output. Thereby, in the control circuit, when there is no detection output, the switching phase of the second switch is controlled to obtain the ID detection output, and the specific content of the asynchronous state can be determined.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A color signal (including a burst signal) is supplied to an input terminal 21 and guided to a phase detector 22 and an ID detector 26 . On the other hand, 23 is
It is a crystal voltage controlled oscillator, and the first and second carriers R
Outputs 1 and R2.

The carriers R1 and R2 have a phase difference of 90'' from each other and are supplied to the switches 24 and 25.

The switch 24 selects the carriers 24 and 25 every horizontal period and supplies the selected output to the I-th detector 22 . The phase detector 22 compares the phases of the human burst signal and the carrier, and supplies the phase error to the oscillation phase control terminal of the voltage controlled oscillator 23.

Phases of carriers R1 and R2 and burst signals CBI and C
The relationship with the phase of B2 is set as shown in FIG. 2(A) in a normal state where the system and the burst signal are synchronized.

That is, for one burst signal CB2, carrier R
2 is set at a phase position of approximately 90@, and carrier R1 is set at a phase position of approximately 180@.

Here, the switch 24 is set to select carrier R1 for burst signal BCI, and select carrier R2 for burst signal CB2. The phase detector 22 obtains a constant DC output when the phase difference between the two input signals is 90''.Thereby, this loop performs phase control such that the burst signal and the carrier are always stabilized at a phase difference of 90 degrees. Get the behavior.

On the other hand, switch 25 is set to select carrier R2 for burst signal CBI and select carrier R1 for burst signal CB2.

With this phase relationship, if there are both human power signals, the ID
The detector 26 obtains an ID detection output as shown in FIG. 2(B). Then, as the base 1111D pulse REF-10, a pulse as shown in FIG. Reference ID pulse REr'
-10 is obtained by slicing the positive side of the detection output at the reference level Vrefl, and ID pulse ID is obtained by slicing the negative side of the detection output at the reference level Vrer2.

This reference ID pulse REF-ID and ID pulse ID
is supplied to switch 27. Here, the switch 27 alternately selects the reference ID pulse REF-ID and the ID pulse ID for each IH according to the control signal shown in FIG. 2(E) and outputs each to the first and second output sections. To,
A pulse for each IH is derived from one output section as shown in FIG. 2(F), and no output is obtained from the other output section as shown in FIG. 2(G).

If the phases of the switches 24, 25, and 26 are reversed for some reason, the ID
A positive pulse-like detection output is obtained from the detector 26 for each IH. As a result, the reference ID pulse REP-ID and the ID pulse ID become as shown in FIGS. 3(B) and 3(C). FIG. 3(C) shows the control signal for the switch 27 at this time. The switch 27 is a reference ID pulse for each IH! ? Since the EF-ID and ID pulse ID sides are alternately selected and outputted to the first and second output sections, the signals from each output section end up being pulses every 2H (see Figure 3). (E), Figure 3 (F)).

The output of the switch 27 is supplied to a control circuit 28, and the control circuit 28 logically determines the output of the switch 27, determines whether the system operation is normally synchronized, and determines whether the system is in a normal state or not. The switching phases of switches 24, 25, and 27 are controlled so that

According to the above embodiment, an ID detection output can be obtained both when the switch phase of the system is in reverse phase and when it is in positive phase. This allows the control circuit 28 to immediately switch the switch phase.

When the switch phase is changed as described above, if the phase relationship between the burst signal and the carrier is as shown in Figure 2 (A), sufficient ID detection output can be obtained as described above. .

However, if the phases of the burst signal and the carrier are not in a positive or negative phase relationship, but are out of phase, a detection output of a sufficient level may not be obtained. Even in such a case, this embodiment is configured to control the operation of the switch 27 to forcibly obtain an ID detection output, so that it can be determined whether the phase is positive or negative.

That is, the control circuit 28 is configured to invert the polarity of the switch 25 for a period of 2H when no pulse is input from the switch 27. Then, since an ID detection output is obtained, the output state of the pulse is determined, and a determination is made as to whether the pulse is in positive phase or in negative phase.

Hereinafter, the principle of operation when the level of the ID detection output is small will be explained with reference to FIGS. 4 and 5.

FIG. 4 shows a case where the switching phase of the system is matched, but the carrier phase is shifted due to the operation of the APC loop.

FIG. 4(A) shows the phase of the burst signal. 4B shows the selected state of the switch 25, and FIG. 2C shows the phases of the carriers R1 and R2 output from the switch 25. Figure (D) shows the ID detection output, and due to the operation of the APC loop, the phase difference between the burst signal and the carrier is 01-0'', θ1-90' θl-18
0”.Furthermore, in the same figure (E),
The switching mode of the third switch 27 is shown, and (F) in the same figure shows the pulse waveforms of the first and second output sections output from the switch 27.

A more detailed explanation is as follows.

In the case of θ1-0', as shown in FIGS.
ID) pulse appears. This is because the burst signal and carrier are compared alternately in the 09 and 180'' states.

In the case of θ1-90° (solid line state), no ID detection output appears. The control circuit determines this and switches switch 2.
Try shifting the phase of No. 5 by IH as shown by the dotted line.

Then, since the output of the switch 25 has the phase indicated by the dotted line, the output section of the switch 27 receives pulses of (+ID) and (-1, D) from the first and second output sections at a 2H period, respectively. appear alternately. This is because phase comparison between the burst signal and carrier in the ID detector 26 is performed at 180'' and 90'' for each IH.

In the case of θl-180'' (opposite phase relationship to the case at 0')
The output section of the switch 27 receives I from only the second output section.
A (-1D) pulse appears at H period.

5(A) to (F) similarly show the phase relationship between the burst signal and the carrier, the selection state of each switch, the output of the switch 27, and the locked state of the APC loop at 0''9.
The case of 0"180" is shown separately. The example shown in FIG. 5 is a case where the switching phase of the system is of opposite polarity.

In the case of θ1-0'' (phase relationship shown by the solid line), the ID detection output does not appear. Therefore, when the control circuit shifts the switching phase of the switch 25 as shown by the dotted line, the carrier is in the phase shown by the dotted line. As a result of the comparison, a detection output appears, but as seen in the output of the switch 27, a (-1D) pulse appears only from the second output section at the IH period.

In the case of θL-90'', the ID detection output appears, but depending on the selection of the switch 27, (
Pulses of 10ID) and (-1D) appear.

In the case of θl-180°, the carrier is always 90'' for the burst signal at first, and no ID detection output appears.The control circuit determines this and switches switch 25.
Let's control the phase and set it to the phase shown by the dotted line. Then, the detection output can be obtained, but in this case, (+I
Only the pulse D) appears.

The following can be understood from the operation modes shown in FIGS. 4 and 5 above.

■If there is no ID detection output, try controlling the phase of switch 25 to obtain (+ID) and (
-1D) pulses are obtained alternately (DAI 4th
θ1-90' in the figure, 01-〇'' in Figure 5 θ1-180
” example), the system switching phase is correct, but A
The problem is that the pull-in in the PC loop is out of alignment.

In this case, it is sufficient to wait until the APC loop is closed.

Next, try controlling the phase of the switch and if only (-1D) or (+ID) is obtained (01-1 in Figure 5).
80 @ example), in this case, the switching phase of the system is reversed, so switches 24, 25, 27
It is necessary to reverse the switching phase.

■If (+ID) and (-1D) pulses are obtained alternately from the beginning, the switching phase of the system is reversed, and it is necessary to reverse the switching phase of switches 24, 25, and 27. be.

(2) If only (-1D) pulses are obtained from the beginning (example of θ1-180° in FIG. 4), the pull-in in the APC loop is out of alignment.

In this case, it is sufficient to wait until the APC loop is closed.

The means for determining whether the switching phase state of the system is in positive phase or in negative phase using the output of the switch 27 is as follows:
Various embodiments are possible.

FIG. 6 shows a specific example of the control circuit 28.

The input terminals 31 and 32 receive the reference ID from the ID detector 26.
Pulse REF-10 and ID pulse ID are each supplied and guided to switch 27.

The switch 27 is switched and controlled by a D-type flip-flop circuit 47 that operates using the horizontal pulse fH as a clock. The flip-flop circuit 47 is connected to the switch 4
The data output phase can be inverted depending on the selection state of No. 5. This is because when the switch 45 is controlled by the output of the AND circuit 43 via the inversion circuit 44, the output of the flip-flop circuit 47 can be taken in directly or via the inversion circuit 46.

From the switch 27, outputs of (+ID) and (-1D) are obtained at the first output section and the second output section. This switch output is transmitted to the first and second flip-flop circuits 33.
34 sets are supplied to the manpower department. The flip-flop circuits 33 and 34 are reset by the horizontal pulse fH. The output of the flip-flop circuit 33 is an OR circuit 35
The signal is supplied to the AND circuit 38 via the AND circuit 5 as well as to the AND circuit 5. Further, the output of the flip-flop circuit 34 is supplied to an OR circuit 35 and also to an AND circuit 36.

The AND circuit 36 includes a D type flip-flop circuit 4
A zero output is also provided. The output of the AND circuit 36 is
It is supplied to a D-type flip-flop circuit 37. This flip-flop circuit 37 also operates using the horizontal pulse fH as a clock. The output of the flip-flop circuit 37 is supplied to an AND circuit 38, 41 and an OR circuit 42. The output of the OR circuit 35 and the inverted output of the D-type flip-flop circuit 40 are supplied to the AND circuit 38 , and the output of the AND circuit 38 is supplied to the OR circuit 39 . The output of the AND circuit 55 is also supplied to the three OR circuits.

The output of the OR circuit 40 is supplied to a D-type flip-flop circuit 40, and the output of this D-type flip-flop circuit 40 is supplied to AND circuits 41, 43, and the like. The output of a D-type flip-flop circuit 57 is also supplied to the AND circuit 41.

The AND circuit 53 is supplied with the output of the AND circuit 55 and the output of the flip-flop circuit 33, and its output is supplied to the set input section of the flip-flop circuit 52. The output of the flip-flop circuit 52 is used to switch the switch 50, and in the reset state, the state is as shown in the figure.

The reset input section of the flip-flop circuit 52 is supplied with the output of the flip-flop circuit 57 via the inverting circuit 51 .

The output of the flip-flop circuit 57 is supplied to AND circuits 54 and 55. The AND circuit 54 is supplied with the output of the flip-flop circuit 40 and the output of the OR circuit 35. Further, the output of the flip-flop circuit 57 and the output of the flip-flop circuit 40 are supplied to the AND circuit 55. The output of the AND circuit 54 is supplied to the OR circuit 56, and the output of the AND circuit 55 is supplied to the OR circuit 5.
6, an AND circuit 53, and an OR circuit 39. The output of the OR circuit 56 is supplied to a flip-flop circuit 57.

The output of the flip-flop circuit 57 can control the switch 25 via the inverting circuit 61. switch 2
5 can thereby reverse or rotate the switching phase. The state of the switch in the figure shows a controlled state of "1".

7 and 8 are timing charts shown to explain the operation of the above circuit.

Figure 7 shows a pulse of (+ID) or (-ID).
This is the operation when a pulse of 1 is obtained from the switch 27. In this case, the outputs of the flip-flop circuits 52 and 57 are O''. FIG. 7<A) is the reference timing waveform of the vine system. FIG.
D) is the pulse.

The output pulse from switch 27 is (-1D).

If (-1D), (-1D), etc. are obtained continuously, the output of the flip-flop circuit 37 rises at the first (-1D) ((C) in the same figure), and then at the next (-1D). The output of the flip-flop circuit 40 rises. If the next value is also (-1D), a system phase inversion pulse PI is obtained, and the system phase inversion is performed.

Next, when a pulse that repeats (-1D), (+ID), (-1D), etc. is input, the output of the flip-flop circuit 40 rises at the same time as the (-1D) (3rd) pulse. The output of circuit 37 falls. Then, the inversion operation of the flip-flop circuit 47 is 1
The polarity of the switch 25 is reversed. FIG. 7(E) shows the output of the flip-flop circuit 47.

FIG. 8 is a timing chart shown to explain the operation when there is no rD detection output at first. FIG. 7(A) is a reference timing waveform of the system.

In this case, the output of the flip-flop circuit 57 rises ((B) in the figure). Then, Figures 4 and 5
As shown, the switching phase of switch 25 is reversed. As a result, when (-1D) is obtained first, the output of the flip-flop circuit 40 rises, and the next time (-1D) is obtained.
-1D), the polarity of the flip-flop circuit 47 is inverted. Also, from the state where there is no ID detection output,
If (+ID) and (10ID) are obtained consecutively,
After the switching phase of switch 25 is reversed, the first (+
ID), the output of the flip-flop circuit 40 rises, and the flip-flop circuit 52 is also set (FIG. 8(E)). Then, when (+ID) is obtained the next time, the polarity of the flip-flop circuit 47 is inverted. This can be seen by changing the polarity of the switch 25 for the next two horizontal periods when there is no ID detection output.
-1D).

Is it a pattern of (-1D)?(+I D), (+
This means that the pattern ID) has been detected.

[Effects of the Invention] As explained above, the present invention has a means for obtaining a detection output by switching the phase of the input signal of the ID detector even when the ID detection output is absent or small. The state of the system phase can be determined from the output, and system synchronization can be achieved at high speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIGS. 2 to 5 are signal waveform diagrams shown to explain the operation of the circuit of this invention, and FIG. 6 is the control circuit of FIG. 1. 7 and 8 are signal waveform diagrams shown to explain the operation of the circuit in FIG. 6, FIG. 9 is a diagram showing a conventional automatic phase control circuit, and FIG. This figure and FIG. 11 are explanatory diagrams of the operation of the circuit of FIG. 9. 22... Phase detector, 23... Voltage controlled token vibrator,
24.25.27...Switch, 26...ID detector, 28...Control circuit.

Claims (1)

[Claims] (1) The first carrier and this first carrier and approximately 9
a voltage-controlled oscillator that obtains a second carrier with a 0° phase difference; a first switch that alternately switches and derives the first and second carriers at a predetermined period; The first switch is in opposite phase to the first switch.
and a second switch that alternately switches and derives the second carrier, and compares the phase of the burst signal that arrives with the phase alternately switching by approximately 90 degrees at the predetermined period and the output of the first switch. , a first phase detection that performs phase control of the voltage controlled oscillator based on the phase error output; and a first and second output section that performs a phase comparison between the output of the second switch and the burst signal. a second phase detector that outputs a phase detection output at the predetermined period, and phase detection outputs of the first and second output sections of the second phase detector are alternately selected at the predetermined period. and a third switch that leads to the first and second output parts, respectively, and the logic contents of the first and second output parts of this third switch are determined, and if there is no output in any of them, , determine the system phase synchronization state with respect to the burst signal by controlling the switching phase of the second switch to obtain a logic output, and fix or reverse the phase of the synchronous switching operation of the first to third switches. and a control circuit for controlling, and when the first and second carriers having a phase difference of 90 degrees are made to correspond to a burst signal having a phase difference of 90 degrees,
An automatic phase control circuit characterized in that in the second phase detector during normal operation, the phase relationship is set to be 90° and 180° with respect to the burst signal of one phase.