JPS62187876U - - Google Patents

Info

Publication number
JPS62187876U
JPS62187876U JP7683686U JP7683686U JPS62187876U JP S62187876 U JPS62187876 U JP S62187876U JP 7683686 U JP7683686 U JP 7683686U JP 7683686 U JP7683686 U JP 7683686U JP S62187876 U JPS62187876 U JP S62187876U
Authority
JP
Japan
Prior art keywords
package body
dummy
terminal
power supply
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7683686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7683686U priority Critical patent/JPS62187876U/ja
Publication of JPS62187876U publication Critical patent/JPS62187876U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の半導体パツケージの実施例を
示す平面図、第2図はダミーパターンを拡大して
示す図、第3図は基板実装状態を示す平面図であ
る。 第1図において、2は電源端子、3はダミー端
子、4はダミーパターン、5はパツケージ本体で
ある。
FIG. 1 is a plan view showing an embodiment of the semiconductor package of the present invention, FIG. 2 is an enlarged view of a dummy pattern, and FIG. 3 is a plan view showing a state where the semiconductor package is mounted on a board. In FIG. 1, 2 is a power supply terminal, 3 is a dummy terminal, 4 is a dummy pattern, and 5 is a package body.

Claims (1)

【実用新案登録請求の範囲】 パツケージ本体5に正規の電源端子2と共にそ
れと同一種類のダミー端子3を突設し、 それら両端子2,3の間のパツケージ本体5表
面に、実装基板シヨートテスト後に半田付け接続
するダミーパターン4を設ける半導体パツケージ
[Claims for Utility Model Registration] A dummy terminal 3 of the same type as the regular power supply terminal 2 is provided protruding from the package body 5, and the surface of the package body 5 between the terminals 2 and 3 is soldered after the mounting board short test. A semiconductor package provided with a dummy pattern 4 to be attached and connected.
JP7683686U 1986-05-20 1986-05-20 Pending JPS62187876U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7683686U JPS62187876U (en) 1986-05-20 1986-05-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7683686U JPS62187876U (en) 1986-05-20 1986-05-20

Publications (1)

Publication Number Publication Date
JPS62187876U true JPS62187876U (en) 1987-11-30

Family

ID=30924285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7683686U Pending JPS62187876U (en) 1986-05-20 1986-05-20

Country Status (1)

Country Link
JP (1) JPS62187876U (en)

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