JPS62183442U

JPS62183442U -

Info

Publication number: JPS62183442U
Application number: JP1986070895U
Authority: JP
Priority date: 1986-05-12
Filing date: 1986-05-12
Publication date: 1987-11-20

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による信号断検出
回路を示すブロツク図、第２図はその各部の動作
波形図、第３図は従来の信号断検出回路のブロツ
ク図、第４図はその各部の動作波形図である。図において、２はシングル＝デユアル変換回路
、３はレベルシフト回路、４は正のピーク検出回
路、５は負のピーク検出回路、６は比較回路であ
る。なお、図中、同一符号は同一、又は相当部分
を示す。 Figure 1 is a block diagram showing a signal disconnection detection circuit according to an embodiment of this invention, Figure 2 is an operation waveform diagram of each part thereof, Figure 3 is a block diagram of a conventional signal disconnection detection circuit, and Figure 4 is the same. FIG. 3 is an operation waveform diagram of each part. In the figure, 2 is a single-to-dual conversion circuit, 3 is a level shift circuit, 4 is a positive peak detection circuit, 5 is a negative peak detection circuit, and 6 is a comparison circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

補正昭６１．１２．１１考案の名称を次のように補正する。考案の名称信号断検出回路実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment December 11, 1981 The name of the invention is amended as follows. Title of the invention: Signal disconnection detection circuit The scope of the utility model registration claims and the brief description of the drawings are amended as follows.

【実用新案登録請求の範囲】受信したタイミング信号をデユアル化するシン
グル＝デユアル変換回路と、前記シングル＝デユ
アル変換回路によつてデユアル化された差動出力
信号を所定のレベル差となるようにレベルシフト
するレベルシフト回路と、前記レベルシフト回路
の一方の出力信号波形のＤ．Ｃ．レベルの最大値
を検出する正のピーク検出回路と、前記レベルシ
フト回路のうち前記正のピーク検出回路に入力さ
れていない方の出力信号波形のＤ．Ｃ．レベルの
最小値を検出する負のピーク検出回路と、前記正
のピーク検出回路の出力信号と前記負のピーク検
出回路の出力信号の比較を行う比較回路とを備え
た信号断検出回路。[Claims for Utility Model Registration] A single-to-dual conversion circuit that dualizes a received timing signal; and a differential output signal dualized by the single-to-dual conversion circuit, which is leveled to have a predetermined level difference. D. of the level shift circuit to be shifted and the output signal waveform of one of the level shift circuits . C. D. of the output signal waveform of the positive peak detection circuit that detects the maximum level value and the output signal waveform of the level shift circuit that is not input to the positive peak detection circuit . C. A signal loss detection circuit comprising: a negative peak detection circuit that detects a minimum level value; and a comparison circuit that compares an output signal of the positive peak detection circuit and an output signal of the negative peak detection circuit.

【図面の簡単な説明】第１図はこの考案の一実施例による信号断検出
回路を示すブロツク図、第２図はその各部の動作
波形図、第３図は従来の信号断検出回路のブロツ
ク図、第４図はその各部の動作波形図である。図において、２はシングル＝デユアル変換回路
、３はレベルシフト回路、４は正のピーク検出回
路、５は負のピーク検出回路、６は比較回路であ
る。なお、図中、同一符号は同一、又は相当部分
を示す。[Brief Description of the Drawings] Figure 1 is a block diagram showing a signal disconnection detection circuit according to an embodiment of the present invention, Figure 2 is an operation waveform diagram of each part thereof, and Figure 3 is a block diagram of a conventional signal disconnection detection circuit. 4 are operational waveform diagrams of each part. In the figure, 2 is a single-to-dual conversion circuit, 3 is a level shift circuit, 4 is a positive peak detection circuit, 5 is a negative peak detection circuit, and 6 is a comparison circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

a single-to-dual conversion circuit for dualizing the received timing signal; a level shift circuit for level-shifting the differential output signal dualized by the single-to-dual conversion circuit to a predetermined level difference; a positive peak detection circuit that detects the maximum value of the D and C levels of one output signal waveform of the level shift circuit; and a positive peak detection circuit that detects the maximum value of the D and C levels of the output signal waveform of one of the level shift circuits; A signal disconnection detection circuit comprising a negative peak detection circuit that detects the minimum value of D and C levels, and a comparison circuit that compares the output signal of the positive peak detection circuit and the output signal of the negative peak detection circuit. .