JPS62180949U - - Google Patents
Info
- Publication number
- JPS62180949U JPS62180949U JP1986069134U JP6913486U JPS62180949U JP S62180949 U JPS62180949 U JP S62180949U JP 1986069134 U JP1986069134 U JP 1986069134U JP 6913486 U JP6913486 U JP 6913486U JP S62180949 U JPS62180949 U JP S62180949U
- Authority
- JP
- Japan
- Prior art keywords
- package
- storage chamber
- view
- semiconductor pellet
- bump electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000008188 pellet Substances 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図及び第２図は本考案の一実施例である半
導体装置を示し、第１図は一部を断面にした斜視
図、第２図は断面図である。第３図乃至第９図は
第１図及び第２図に示す半導体装置の製造工程を
説明する図で、第３図はリードフレームの平面図
、第４図は折り曲げ整形したリードフレームの側
面図、第５図は樹脂モールドしたリードフレーム
の平面図、第６図は第５図中のＡ―Ａ線に沿う断
面図、第７図はリードフレームの樹脂モールド部
分の斜視図、第８図はタイバーの切断除去を容易
にするためのパツケージに設けられる空洞を示す
斜視図、第９図はパツケージに蓋を被着する工程
を示す断面図である。第１０図及び第１１図は本
考案の他の実施例のパツケージを夫々示す断面図
である。第１２図乃至第１５図は従来例を示し、
第１２図は半導体装置の斜視図、第１３図はリー
ドフレームの平面図、第１４図は半導体ペレツト
を載置したリードフレームの平面図、第１５図は
樹脂モールドされたリードフレームの平面図であ
る。
１０……半導体装置、１１……パツケージ、１
２……収納室、１３……リード、１４……半導体
ペレツト、１５……バンプ電極、１６……蓋。
1 and 2 show a semiconductor device which is an embodiment of the present invention, with FIG. 1 being a partially sectional perspective view and FIG. 2 being a sectional view. 3 to 9 are diagrams explaining the manufacturing process of the semiconductor device shown in FIGS. 1 and 2. FIG. 3 is a plan view of the lead frame, and FIG. 4 is a side view of the bent and shaped lead frame. , FIG. 5 is a plan view of a resin-molded lead frame, FIG. 6 is a sectional view taken along the line AA in FIG. 5, FIG. 7 is a perspective view of the resin-molded portion of the lead frame, and FIG. FIG. 9 is a perspective view showing a cavity provided in the package cage to facilitate cutting and removal of the tie bars, and FIG. 9 is a sectional view showing the process of attaching a lid to the package cage. FIGS. 10 and 11 are sectional views showing packages according to other embodiments of the present invention, respectively. 12 to 15 show conventional examples,
FIG. 12 is a perspective view of a semiconductor device, FIG. 13 is a plan view of a lead frame, FIG. 14 is a plan view of a lead frame on which a semiconductor pellet is placed, and FIG. 15 is a plan view of a resin-molded lead frame. be. 10...Semiconductor device, 11...Package, 1
2... Storage chamber, 13... Lead, 14... Semiconductor pellet, 15... Bump electrode, 16... Lid.
Claims (1)
製のパツケージと、 一端が上記収納室の底面に露呈し、他端がパツ
ケージの外表面に露呈するようにパツケージ内に
埋め込まれたリードと、 バンプ電極を有し、このバンプ電極が上記リー
ドの一端に接続された状態で上記収納室の底面に
載置固定された半導体ペレツトと、 上記収納室開口を封止するようにパツケージの
天面に被着した蓋とからなることを特徴とする半
導体装置。[Scope of Claim for Utility Model Registration] A package made of resin mold having a storage chamber with an open top, and a package inside the package so that one end is exposed to the bottom surface of the storage chamber and the other end is exposed to the outer surface of the package cage. a semiconductor pellet having a lead embedded in the semiconductor pellet and a bump electrode, the semiconductor pellet being placed and fixed on the bottom surface of the storage chamber with the bump electrode connected to one end of the lead, and sealing the opening of the storage chamber. A semiconductor device comprising a lid attached to the top surface of a package cage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986069134U JPS62180949U (en) | 1986-05-08 | 1986-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986069134U JPS62180949U (en) | 1986-05-08 | 1986-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62180949U true JPS62180949U (en) | 1987-11-17 |
Family
ID=30909579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986069134U Pending JPS62180949U (en) | 1986-05-08 | 1986-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62180949U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252154A (en) * | 1986-04-24 | 1987-11-02 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2011060889A (en) * | 2009-09-08 | 2011-03-24 | Tokai Rika Co Ltd | Package with electronic component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191668A (en) * | 1975-02-10 | 1976-08-11 | Shusekikairosochi no kumitatehoho |
-
1986
- 1986-05-08 JP JP1986069134U patent/JPS62180949U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191668A (en) * | 1975-02-10 | 1976-08-11 | Shusekikairosochi no kumitatehoho |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252154A (en) * | 1986-04-24 | 1987-11-02 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2011060889A (en) * | 2009-09-08 | 2011-03-24 | Tokai Rika Co Ltd | Package with electronic component |